Patch set updated for coreboot: d71a49b amd/dinar: Eliminate compiler warnings from build
Paul Menzel (paulepanter@users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3545
-gerrit
commit d71a49b73df697967981436d68a614a5aa0e32bd Author: Bruce Griffith Bruce.Griffith@se-eng.com Date: Tue Jun 25 14:02:41 2013 -0600
amd/dinar: Eliminate compiler warnings from build
Fix a bunch of compiler-generated warning messages. These fixes are mainly copied into AMD Family 15 server boards from similar code in AMD Family 15tn (Trinity) boards.
Change-Id: I93cef8899170b5575e7fb7c55181b381a7bcd9d8 Signed-off-by: Bruce Griffith Bruce.Griffith@se-eng.com --- src/mainboard/amd/dinar/BiosCallOuts.c | 1 - src/mainboard/amd/dinar/agesawrapper.c | 19 +++-- src/mainboard/amd/dinar/agesawrapper.h | 4 +- src/mainboard/amd/dinar/buildOpts.c | 132 +++++++++++++++++++++++++-------- src/mainboard/amd/dinar/romstage.c | 2 + 5 files changed, 117 insertions(+), 41 deletions(-)
diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 4fb3c66..c9888b9 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -584,7 +584,6 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) UINT32 GpioMmioAddr; UINT8 Data8; UINT16 Data16; - UINT8 TempData8;
FcnData = Data; MemData = ConfigPtr; diff --git a/src/mainboard/amd/dinar/agesawrapper.c b/src/mainboard/amd/dinar/agesawrapper.c index 4017adc..179822b 100644 --- a/src/mainboard/amd/dinar/agesawrapper.c +++ b/src/mainboard/amd/dinar/agesawrapper.c @@ -75,6 +75,8 @@ VOID *AcpiAlib = NULL; * L O C A L F U N C T I O N S *--------------------------------------------------------------------------------------- */ +extern VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); +extern VOID OemCustomizeInitPost(IN AMD_POST_PARAMS *InitPost);
/*Get the Bus Number from CONFIG_MMCONF_BUS_NUMBER, Please reference AMD BIOS BKDG docuemt about it*/ /* @@ -88,6 +90,7 @@ Bits Buses Bits Buses 3h 8 8h 256 4h 16 Fh-9h Reserved */ +STATIC UINT8 GetEndBusNum ( VOID @@ -283,9 +286,12 @@ agesawrapper_amdinitreset ( ) { AGESA_STATUS status; +#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) AMD_INTERFACE_PARAMS AmdParamStruct; AMD_RESET_PARAMS AmdResetParams; +#endif
+#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) LibAmdMemFill (&AmdParamStruct, 0, sizeof (AMD_INTERFACE_PARAMS), @@ -307,12 +313,13 @@ agesawrapper_amdinitreset ( AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); -#endif - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(); AmdReleaseStruct (&AmdParamStruct); +#else + status = AGESA_SUCCESS; +#endif + return (UINT32)status; }
@@ -432,8 +439,6 @@ agesawrapper_amdinitenv ( { AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - PCI_ADDR PciAddress; - UINT32 PciValue;
LibAmdMemFill (&AmdParamStruct, 0, @@ -574,11 +579,11 @@ agesawrapper_amdlaterunaptask ( ) { AGESA_STATUS Status; - AMD_LATE_PARAMS AmdLateParams; + AP_EXE_PARAMS AmdLateParams;
LibAmdMemFill (&AmdLateParams, 0, - sizeof (AMD_LATE_PARAMS), + sizeof (AP_EXE_PARAMS), &(AmdLateParams.StdHeader));
AmdLateParams.StdHeader.AltImageBasePtr = 0; diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 0b4a701..62fd277 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -126,11 +126,9 @@ UINT32 agesawrapper_amdinitenv (void); UINT32 agesawrapper_amdinitlate (void); UINT32 agesawrapper_amdinitpost (void); UINT32 agesawrapper_amdinitmid (void); -void sb_After_Pci_Init (void); -void sb_Mid_Post_Init (void); -void sb_Late_Post (void); UINT32 agesawrapper_amdreadeventlog (void); UINT32 agesawrapper_amdinitmmio (void); void *agesawrapper_getlateinitptr (int pick); +UINT32 agesawrapper_amdlaterunaptask (UINT32 Data, VOID *ConfigPtr);
#endif diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 1d57d7a..41f5415 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -36,13 +36,39 @@ #include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE - +//#define OPTION_HW_DQS_REC_EN_TRAINING TRUE +/* AGESA will check the OEM configuration during preprocessing stage, + * coreboot enable -Wundef option, so we should make sure we have all contanstand defined + */ +/* MEMORY_BUS_SPEED */ +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency + +/* QUANDRANK_TYPE */ +#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM +#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM + +/* USER_MEMORY_TIMING_MODE */ +#define TIMING_MODE_AUTO 0 ///< Use best rate possible +#define TIMING_MODE_LIMITED 1 ///< Set user top limit +#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed + +/* POWER_DOWN_MODE */ +#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode +#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
/* Select the cpu family. */
/* Select the cpu socket type. */ -#define INSTALL_G34_SOCKET_SUPPORT TURE +#define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE #define INSTALL_S1G4_SOCKET_SUPPORT FALSE @@ -211,17 +237,41 @@ */ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + { //BUID Swap List + { //BUID Swaps + /* Each Non-coherent chain may have a list of device swaps, + * Each item specify a device will be swap from its current id to a new one + */ + /* FromID 0x00 is the chain with the southbridge */ + /* 'Move' device zero to device zero, All others are non applicable */ + {0x00, 0x00}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, {0xFF, 0xFF}, + }, + + { //The ordered final BUIDs + /* Specify the final BUID to be zero, All others are non applicable */ + 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, + } + } + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } };
#define BLDCFG_BUID_SWAP_LIST &MaranelloManualBuidSwapList @@ -236,20 +286,32 @@ CONST MANUAL_BUID_SWAP_LIST ROMDATA MaranelloManualBuidSwapList[2] =
CONST CPU_TO_CPU_PCB_LIMITS ROMDATA MaranelloCpuToCpuLimitList[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, - HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, these settings apply to all coherent links */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set incoming and outgoing links to 16 bit widths, and 3.2GHz frequencies */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + { + HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } };
#define BLDCFG_HTFABRIC_LIMITS_LIST &MaranelloCpuToCpuLimitList
// A performance-per-watt optimization. CONST SKIP_REGANG ROMDATA PerfPerWatt[] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF, - HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF, - HT_LIST_TERMINAL, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, POWERED_OFF }, + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, HT_LIST_MATCH_ANY, HT_LIST_MATCH_INTERNAL_LINK, POWERED_OFF }, + { HT_LIST_TERMINAL } };
// uncomment the line below to make Perf-per-watt enabled by default. @@ -258,8 +320,18 @@ CONST SKIP_REGANG ROMDATA PerfPerWatt[] = {
CONST IO_PCB_LIMITS ROMDATA MaranelloIoLimitList[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, - HT_LIST_TERMINAL + { + /* On the reference platform, there is only one nc chain, so socket & link are 'don't care' */ + HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + + /* Set upstream and downstream links to 16 bit widths, and limit frequencies to 3.2GHz */ + HT_WIDTH_16_BITS, HT_WIDTH_16_BITS, HT_FREQUENCY_LIMIT_2600M, //Actually IO hub only support 2600M MAX + }, + + /* The 2nd element in the array merely terminates the list */ + { + HT_LIST_TERMINAL, + } };
#define BLDCFG_HTCHAIN_LIMITS_LIST &MaranelloIoLimitList @@ -283,9 +355,9 @@ CONST SYSTEM_PHYSICAL_SOCKET_MAP ROMDATA DinarPhysicalSocketMap[] = CONST OVERRIDE_BUS_NUMBERS ROMDATA MaranelloOverrideBusNumbers[5] = { // Socket, Link, SecBus, SubBus - 0, 2, 0x00, 0xBF, // RD890 of Dinar - 1, 0, 0xC0, 0xFF, // HTX - HT_LIST_TERMINAL + { 0, 2, 0x00, 0xBF }, // RD890 of Dinar + { 1, 0, 0xC0, 0xFF }, // HTX + { (HT_LIST_TERMINAL) } };
#define BLDCFG_BUS_NUMBERS_LIST &MaranelloOverrideBusNumbers @@ -295,7 +367,7 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_200M, HT_FREQUENCY_1800M, DeemphasisLevelNone, DcvLevelNone}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2000M, HT_FREQUENCY_2600M, DeemphasisLevelMinus3, DcvLevelMinus3}, { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_FREQUENCY_2800M, HT_FREQUENCY_MAX, DeemphasisLevelMinus6, DcvLevelMinus6}, - 0xFF + { (0xFF) } };
#define BLDCFG_PLATFORM_DEEMPHASIS_LIST DinarDeemphasisList @@ -314,9 +386,9 @@ CONST CPU_HT_DEEMPHASIS_LEVEL ROMDATA DinarDeemphasisList[] = */ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = { - HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, - 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, {0}, - HT_LIST_TERMINAL + { HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, HT_LIST_MATCH_ANY, + 0, 0, HT_LIST_MATCH_ANY, {0, 0, 0, 0, 0, 1, 0}, 0, 0, 0, 0, 0 }, + { (HT_LIST_TERMINAL) } };
#define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 77f73e2..e52b5f7 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -41,6 +41,8 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +void disable_cache_as_ram(void); + u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); u32 agesawrapper_amdinitearly (void);
-
Paul Menzel