Change in ...coreboot[master]: mb/google/sarien/variants/sarien: Set up tcc offset for sarien
John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30808
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien. Refer to b:122636962#comment1
BUG=b:122636962 TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30808/1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index b590bac..8c7e6b3 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -71,6 +71,9 @@ #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "3" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = {
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG@10 PS1, Line 10: 122636962
please add me in this bug for better understanding. Thanks.
I think that come from the UEFI side. But I think you guys may not need to mention comment1 and bug number in commit summary.
https://review.coreboot.org/#/c/30808/1/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/#/c/30808/1/src/mainboard/google/sarien/variants... PS1, Line 75: 3
How did you arrive to this number ? Is this tested with some scenario ?
I will assume that's same as UEFI
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 1: Code-Review+1
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30808/1/src/mainboard/google/sarien/variants... File src/mainboard/google/sarien/variants/sarien/devicetree.cb:
https://review.coreboot.org/#/c/30808/1/src/mainboard/google/sarien/variants... PS1, Line 75: 3
I will assume that's same as UEFI
https://partnerissuetracker.corp.google.com/issues/122636962#comment5
Because this project is follow other project, and will also use the same setting, other's project Tcc offset is 3, so we need to follow the same setting for test ,thank you.
Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG@1 PS1, Line 1: Parent: 4b2553ee (soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TO) Again, please remove the bug number from summary, only leave that in BUG=b.122636962.Thanks
Chris Zhou has uploaded a new patch set (#2) to the change originally created by John Su. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien.
BUG=b:122636962 TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su john_su@compal.corp-partner.google.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30808/2
Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 2: Code-Review+2
Chris Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30808/1//COMMIT_MSG@1 PS1, Line 1: Parent: 4b2553ee (soc/intel/cannonlake: complete rename of TCO2_STS_SECOND_TO)
Again, please remove the bug number from summary, only leave that in BUG=b.122636962. […]
Done
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30808 )
Change subject: mb/google/sarien/variants/sarien: Set up tcc offset for sarien ......................................................................
mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien.
BUG=b:122636962 TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203 Signed-off-by: John Su john_su@compal.corp-partner.google.com Reviewed-on: https://review.coreboot.org/c/30808 Reviewed-by: Duncan Laurie dlaurie@chromium.org Reviewed-by: Lijian Zhao lijian.zhao@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Lijian Zhao: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 37ef3dc5..4334c45 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -74,6 +74,9 @@ #| I2C1 | Touchpad | #| I2C4 | H1 TPM | #+-------------------+---------------------------+ + + register "tcc_offset" = "3" + register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = {
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Chris Zhou (Code Review) -
Duncan Laurie (Code Review)
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John Su (Code Review)
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Lijian Zhao (Code Review)