John Su has uploaded this change for review.
mb/google/sarien/variants/sarien: Set up tcc offset for sarien
Change tcc offset from 15 to 3 for sarien.
Refer to b:122636962#comment1
BUG=b:122636962
TEST=Match the result from TAT UI
Change-Id: I1c5d144e92d1e6e9c81b3e6686805ccf744b7203
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
---
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/30808/1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index b590bac..8c7e6b3 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -71,6 +71,9 @@
#| I2C1 | Touchpad |
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
+
+ register "tcc_offset" = "3"
+
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
.i2c[0] = {
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