Change in coreboot[master]: sb/amd/agesa/hudson: define macros for GNB and IOMMU devices
Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: sb/amd/agesa/hudson: define macros for GNB and IOMMU devices ......................................................................
sb/amd/agesa/hudson: define macros for GNB and IOMMU devices
Following the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 --- M src/southbridge/amd/agesa/hudson/pci_devs.h 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47848/1
diff --git a/src/southbridge/amd/agesa/hudson/pci_devs.h b/src/southbridge/amd/agesa/hudson/pci_devs.h index d67395c..f8a4ca8 100644 --- a/src/southbridge/amd/agesa/hudson/pci_devs.h +++ b/src/southbridge/amd/agesa/hudson/pci_devs.h @@ -7,6 +7,16 @@
#define BUS0 0
+/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) + /* XHCI */ #define XHCI_DEV 0x10 #define XHCI_FUNC 0
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: sb/amd/agesa/hudson: define macros for GNB and IOMMU devices ......................................................................
Patch Set 1:
the definitions look right to me, but those devices aren't in the southbridge/FCH part of the system like the rest of the devices in that file. not sure though how much we care about the separation of northbridge/southbridge in the pre-soc systems
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: sb/amd/agesa/hudson: define macros for GNB and IOMMU devices ......................................................................
Patch Set 1:
Patch Set 1:
the definitions look right to me, but those devices aren't in the southbridge/FCH part of the system like the rest of the devices in that file. not sure though how much we care about the separation of northbridge/southbridge in the pre-soc systems
those two should probably go into src/northbridge/amd/agesa/family15tn/pci_devs.h
Hello build bot (Jenkins), Paul Menzel,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47848
to look at the new patch set (#3).
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Following the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 --- M src/northbridge/amd/agesa/family15tn/pci_devs.h 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47848/3
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
Patch Set 3:
Patch Set 1:
Patch Set 1:
the definitions look right to me, but those devices aren't in the southbridge/FCH part of the system like the rest of the devices in that file. not sure though how much we care about the separation of northbridge/southbridge in the pre-soc systems
those two should probably go into src/northbridge/amd/agesa/family15tn/pci_devs.h
Thank you, done.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
Patch Set 3: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/47848/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47848/3//COMMIT_MSG@9 PS3, Line 9: Following nit: Follow
Hello build bot (Jenkins), Paul Menzel, Angel Pons, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47848
to look at the new patch set (#4).
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Follow the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 --- M src/northbridge/amd/agesa/family15tn/pci_devs.h 1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/47848/4
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47848/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47848/3//COMMIT_MSG@9 PS3, Line 9: Following
nit: Follow
Done.
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47848 )
Change subject: nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices ......................................................................
nb/amd/agesa/family15tn: define macros for GNB and IOMMU devices
Follow the example of newer AMD code for Stoneyridge and Picasso.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I9c17d4cb4953b28a47483f5d7db308ccc89e9281 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47848 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/amd/agesa/family15tn/pci_devs.h 1 file changed, 10 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/northbridge/amd/agesa/family15tn/pci_devs.h b/src/northbridge/amd/agesa/family15tn/pci_devs.h index 22ce8f5..5613843 100644 --- a/src/northbridge/amd/agesa/family15tn/pci_devs.h +++ b/src/northbridge/amd/agesa/family15tn/pci_devs.h @@ -7,6 +7,16 @@
#define BUS0 0
+/* GNB Root Complex */ +#define GNB_DEV 0x0 +#define GNB_FUNC 0 +#define GNB_DEVFN PCI_DEVFN(GNB_DEV, GNB_FUNC) + +/* IOMMU */ +#define IOMMU_DEV 0x0 +#define IOMMU_FUNC 2 +#define IOMMU_DEVFN PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC) + /* Graphics and Display */ #define GFX_DEV 0x1 #define GFX_FUNC 0
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Angel Pons (Code Review) -
Felix Held (Code Review)
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Mike Banon (Code Review)