[S] Change in coreboot[main]: soc/intel/xeon_sp: Add SATC PCI segment group support

[Shuo Liu (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Shuo Liu, Tim Chu.

Shuo Liu has uploaded a new patch set (#7) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/81180?usp=email )

Change subject: soc/intel/xeon_sp: Add SATC PCI segment group support
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soc/intel/xeon_sp: Add SATC PCI segment group support

For every PCI segment group generate a new SATC header.
Allows to generate proper ACPI code when multiple PCI segment
groups are enabled.

TEST=Booted on ibm/sbp1 with multiple PCI segment groups.
      Properly generates multiple SATC headers.
TEST=intel/archercity CRB

Change-Id: I93b8ee05a7e6798e034f7a5da2c6883f0ee7a0e5
Signed-off-by: Patrick Rudolph 
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M src/soc/intel/xeon_sp/uncore_acpi.c
1 file changed, 40 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81180/7