Change in coreboot[master]: nb/intel/sandybridge: Move register headers into a subfolder
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45358 )
Change subject: nb/intel/sandybridge: Move register headers into a subfolder ......................................................................
nb/intel/sandybridge: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Signed-off-by: Angel Pons th3fanbus@gmail.com --- R src/northbridge/intel/sandybridge/registers/host_bridge.h R src/northbridge/intel/sandybridge/registers/mchbar.h M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/45358/1
diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h similarity index 90% rename from src/northbridge/intel/sandybridge/hostbridge_regs.h rename to src/northbridge/intel/sandybridge/registers/host_bridge.h index 2d2fcff..4814b94 100644 --- a/src/northbridge/intel/sandybridge/hostbridge_regs.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ -#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ +#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,4 +60,4 @@
#define DIDOR 0xf3 /* Device ID override, for debug and samples only */
-#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h similarity index 98% rename from src/northbridge/intel/sandybridge/mchbar_regs.h rename to src/northbridge/intel/sandybridge/registers/mchbar.h index 370dd74..2fe6b24 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ -#define __SANDYBRIDGE_MCHBAR_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ +#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__
/* * ### IOSAV memory controller interface poking state machine notes ### @@ -533,4 +533,4 @@ #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ #define CRDTLCK 0x77fc
-#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5318d0b..5c15cb1 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0)
-#include "hostbridge_regs.h" +#include "registers/host_bridge.h"
/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ @@ -66,7 +66,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h"
/* * EPBAR - Egress Port Root Complex Register Block
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45358 )
Change subject: nb/intel/sandybridge: Move register headers into a subfolder ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45358 )
Change subject: nb/intel/sandybridge: Move register headers into a subfolder ......................................................................
nb/intel/sandybridge: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder. Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: Ie525e755f32599db97af7969fc7fbb36a5d826b6 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/45358 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- R src/northbridge/intel/sandybridge/registers/host_bridge.h R src/northbridge/intel/sandybridge/registers/mchbar.h M src/northbridge/intel/sandybridge/sandybridge.h 3 files changed, 8 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/hostbridge_regs.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h similarity index 90% rename from src/northbridge/intel/sandybridge/hostbridge_regs.h rename to src/northbridge/intel/sandybridge/registers/host_bridge.h index 2d2fcff..4814b94 100644 --- a/src/northbridge/intel/sandybridge/hostbridge_regs.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ -#define __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ +#define __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__
#define EPBAR 0x40 #define MCHBAR 0x48 @@ -60,4 +60,4 @@
#define DIDOR 0xf3 /* Device ID override, for debug and samples only */
-#endif /* __SANDYBRIDGE_HOSTBRIDGE_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/registers/mchbar.h similarity index 98% rename from src/northbridge/intel/sandybridge/mchbar_regs.h rename to src/northbridge/intel/sandybridge/registers/mchbar.h index 370dd74..2fe6b24 100644 --- a/src/northbridge/intel/sandybridge/mchbar_regs.h +++ b/src/northbridge/intel/sandybridge/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
-#ifndef __SANDYBRIDGE_MCHBAR_REGS_H__ -#define __SANDYBRIDGE_MCHBAR_REGS_H__ +#ifndef __SANDYBRIDGE_REGISTERS_MCHBAR_H__ +#define __SANDYBRIDGE_REGISTERS_MCHBAR_H__
/* * ### IOSAV memory controller interface poking state machine notes ### @@ -533,4 +533,4 @@ #define CRDTCTL4 0x7410 /* Read Return Tracker credits */ #define CRDTLCK 0x77fc
-#endif /* __SANDYBRIDGE_MCHBAR_REGS_H__ */ +#endif /* __SANDYBRIDGE_REGISTERS_MCHBAR_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 5318d0b..5c15cb1 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -36,7 +36,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0)
-#include "hostbridge_regs.h" +#include "registers/host_bridge.h"
/* Devices 0:1.0, 0:1.1, 0:1.2, 0:6.0 PCI configuration space (PCI Express Graphics) */ @@ -66,7 +66,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or))
/* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h"
/* * EPBAR - Egress Port Root Complex Register Block
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45358 )
Change subject: nb/intel/sandybridge: Move register headers into a subfolder ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 8/1/9 "QEMU x86 q35/ich9" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20202 "QEMU x86 q35/ich9" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20201 "QEMU x86 i440fx/piix4" (x86_64) using payload SeaBIOS : FAIL : https://lava.9esec.io/r/20200 "QEMU x86 i440fx/piix4" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20199 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/20198 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20206 "HP Z220 SFF Workstation" (x86_32) using payload LinuxBoot_BusyBox_kexec : SUCCESS : https://lava.9esec.io/r/20205 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload TianoCore : SUCCESS : https://lava.9esec.io/r/20204 "HP Compaq 8200 Elite SFF PC" (x86_32) using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/20203
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
-
Patrick Georgi (Code Review)
-
Tim Wawrzynczak (Code Review)