Change in coreboot[master]: soc/intel/tigerlake: Add method to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

soc/intel/tigerlake: Add method to modify GPIO community PM config

This patch adds a two helper methods -

1. CGPM to configure GPIO power management bits that are part of
miscellaneous config. This is needed for configuraiton of these bits
based on s0ix entry and exit.

2. GPID to look up GPID community ID for an index. CGPM uses this ID
to configure the appropriate GPIO community

These methods are needed for implementing platform specific workarounds
to modify power management bits on s0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD to check if it is successful"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
---
M src/soc/intel/tigerlake/acpi/gpio.asl
1 file changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40260/1

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index 2b4aff0..ed13468 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -142,3 +142,52 @@
    Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
    Return (Local2)
 }
+
+/*
+ * Return PCR Port ID of GPIO Communities
+ *
+ * Arg0: GPIO Community (0-5)
+ */
+Method (GPID, 1, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (0) {
+			Local0 = PID_GPIOCOM0
+		}
+		Case (1) {
+			Local0 = PID_GPIOCOM1
+		}
+		Case (2) {
+			Local0 = PID_GPIOCOM2
+		}
+		Case (4) {
+			Local0 = PID_GPIOCOM4
+		}
+		Case (5) {
+			Local0 = PID_GPIOCOM5
+		}
+		Default {
+			Return (0)
+		}
+	}
+
+	Return (Local0)
+}
+
+/*
+ * Configure GPIO Power Management bits
+ *
+ * Arg0: GPIO community (0-5)
+ * Arg1: PM bits in MISCCFG
+ */
+Method (CGPM, 2, Serialized)
+{
+	Local0 = GPID (Arg0)
+	If (Local0 != 0) {
+		/* Mask off current PM bits */
+		PCRA (Local0, GPIO_MISCCFG, ~(MISCCFG_ENABLE_GPIO_PM_CONFIG))
+		/* Mask in requested bits */
+		PCRO (Local0, GPIO_MISCCFG,  (Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG))
+	}
+}

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

Patch Set 1: Code-Review+1

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

Patch Set 1: Code-Review+1

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

Patch Set 1:

(2 comments)

https://review.coreboot.org/c/coreboot/+/40260/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40260/1//COMMIT_MSG@9 
PS1, Line 9:  -
:

https://review.coreboot.org/c/coreboot/+/40260/1//COMMIT_MSG@19 
PS1, Line 19: s0ix
S0ix

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

Patch Set 1:

Hm, once again, there's some more copy-paste going on... could we move CGPM to common ?
We could probably move GPID as well, if we can include a SoC-specific header that includes PID_GPIOCOM0, etc.

Change in coreboot[master]: soc/intel/tigerlake: Add methods to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40260

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Add methods to modify GPIO community PM config
......................................................................

soc/intel/tigerlake: Add methods to modify GPIO community PM config

This patch adds a two helper methods -

1. CGPM to configure GPIO power management bits that are part of
miscellaneous config. This is needed for configuraiton of these bits
based on S0ix entry and exit.

2. GPID to look up GPID community ID for an index. CGPM uses this ID
to configure the appropriate GPIO community

These methods are needed for implementing platform specific workarounds
to modify power management bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
---
M src/soc/intel/tigerlake/acpi/gpio.asl
1 file changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40260/2

Change in coreboot[master]: soc/intel/tigerlake: Add methods to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40260

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Add methods to modify GPIO community PM config
......................................................................

soc/intel/tigerlake: Add methods to modify GPIO community PM config

This patch adds a two helper methods:

1. CGPM to configure GPIO power management bits that are part of
miscellaneous config. This is needed for configuraiton of these bits
based on S0ix entry and exit.

2. GPID to look up GPID community ID for an index. CGPM uses this ID
to configure the appropriate GPIO community

These methods are needed for implementing platform specific workarounds
to modify power management bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
---
M src/soc/intel/tigerlake/acpi/gpio.asl
1 file changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40260/3

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 6: Code-Review+1

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG@15 
PS6, Line 15: BUILD
Please be more specific.

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG@11 
PS6, Line 11: configuraiton
configuration

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Duncan Laurie (Code Review)]

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 6:

(1 comment)

https://review.coreboot.org/c/coreboot/+/40260/6/src/soc/intel/common/acpi/g... 
File src/soc/intel/common/acpi/gpio.asl:

https://review.coreboot.org/c/coreboot/+/40260/6/src/soc/intel/common/acpi/g... 
PS6, Line 15: (
shouldn't need () here or in PCRO below

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 6: Code-Review+1

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Hello build bot (Jenkins), Shaunak Saha, Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/40260

to look at the new patch set (#7).

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

soc/intel/common: Add method to modify GPIO community PM config

This patch adds CGPM, a helper method to configure GPIO power management
bits that are part of miscellaneous config. This is needed for
configuration of these bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
---
A src/soc/intel/common/acpi/gpio.asl
1 file changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40260/7

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 7: Code-Review+1

(3 comments)
> Patch Set 6:
>
> (1 comment)

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG@11 
PS6, Line 11: configuraiton
> configuration

Done

https://review.coreboot.org/c/coreboot/+/40260/6//COMMIT_MSG@15 
PS6, Line 15: BUILD
> Please be more specific.

Done

https://review.coreboot.org/c/coreboot/+/40260/6/src/soc/intel/common/acpi/g... 
File src/soc/intel/common/acpi/gpio.asl:

https://review.coreboot.org/c/coreboot/+/40260/6/src/soc/intel/common/acpi/g... 
PS6, Line 15: (
> shouldn't need () here or in PCRO below

Done

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/intel/common: Add method to modify GPIO community PM config

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/common: Add method to modify GPIO community PM config
......................................................................

soc/intel/common: Add method to modify GPIO community PM config

This patch adds CGPM, a helper method to configure GPIO power management
bits that are part of miscellaneous config. This is needed for
configuration of these bits on S0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD volteer and ripto"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40260
Reviewed-by: Venkata Krishna Nimmagadda 
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
A src/soc/intel/common/acpi/gpio.asl
1 file changed, 19 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved
  Venkata Krishna Nimmagadda: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/common/acpi/gpio.asl b/src/soc/intel/common/acpi/gpio.asl
new file mode 100644
index 0000000..364ac73
--- /dev/null
+++ b/src/soc/intel/common/acpi/gpio.asl
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+/*
+ * Configure GPIO Power Management bits
+ *
+ * Arg0: GPIO community (0-5)
+ * Arg1: PM bits in MISCCFG
+ */
+Method (CGPM, 2, Serialized)
+{
+	Local0 = GPID (Arg0)
+	If (Local0 != 0) {
+		/* Mask off current PM bits */
+		PCRA (Local0, GPIO_MISCCFG, ~MISCCFG_ENABLE_GPIO_PM_CONFIG)
+		/* Mask in requested bits */
+		PCRO (Local0, GPIO_MISCCFG,  Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG)
+	}
+}