[S] Change in coreboot[main]: sb/intel/bd82x6x: Make space for USB port config in devicetree

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81878?usp=email )

Change subject: sb/intel/bd82x6x: Make space for USB port config in devicetree
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sb/intel/bd82x6x: Make space for USB port config in devicetree

This is the first step to:

- Move USB port configs, which are static, from C code to devicetree;
- Unify USB port configs between MRC and native code path.

For USB current strength/trace length settings, define one set of
constants that match the selected RAM init code path, so compiler
can produce the correct values for runtime.

This structure will otherwise match the one in C code used by native
code path.

Change-Id: I59af466d41790e2163342cac8676457ac19371ea
Signed-off-by: Keith Hui 
---
M src/southbridge/intel/bd82x6x/chip.h
1 file changed, 15 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/81878/1

diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 66d5cb1..95ca08b 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -5,6 +5,20 @@

#include <southbridge/intel/common/spi.h>
 #include <types.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+/* Shorthands for boards using MRC */
+#if CONFIG(USE_NATIVE_RAMINIT)
+#define USB_GAIN_1 1
+#define USB_GAIN_2 2
+#define USB_GAIN_L 0
+#define USB_GAIN_H 1
+#else
+#define USB_GAIN_1 0x40
+#define USB_GAIN_2 0x80
+#define USB_GAIN_L 0x40
+#define USB_GAIN_H 0x80
+#endif

struct southbridge_intel_bd82x6x_config {
    /**
@@ -77,6 +91,7 @@
    uint32_t spi_uvscc;
    uint32_t spi_lvscc;
    struct intel_swseq_spi_config spi;
+	struct southbridge_usb_port usb_port_config[14];
 };

#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */