Change in coreboot[master]: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters receive from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/1
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..0e7f4fd 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,5 +1,105 @@ chip soc/intel/tigerlake + register "tcc_offset" = "5" # TCC of 95 + + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + # Default DPTF Policy for all Volteer boards if not overridden + chip drivers/intel/dptf + ## Active Policy + register "policies.active[0]" = "{.target=DPTF_CPU, + .thresholds={TEMP_PCT(94, 100), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[2]" = "{.target=DPTF_TEMP_SENSOR_1, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + register "policies.active[3]" = "{.target=DPTF_TEMP_SENSOR_2, + .thresholds={TEMP_PCT(64, 100), + TEMP_PCT(60, 90), + TEMP_PCT(56, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40),}}" + register "policies.active[4]" = "{.target=DPTF_TEMP_SENSOR_3, + .thresholds={TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0), + TEMP_PCT(0, 0),}}" + + ## Passive Policy + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)" + + ## Critical Policy + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN)" + register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits.pl1" = "{ + .min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf[0]" = "{ 255, 1700 }" + register "controls.charger_perf[1]" = "{ 24, 1500 }" + register "controls.charger_perf[2]" = "{ 16, 1000 }" + register "controls.charger_perf[3]" = "{ 8, 500 }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" + register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" + register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" + register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" + register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" + register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" + register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" + register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" + register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" + register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" + + # Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682""
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45111/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45111/1//COMMIT_MSG@10 PS1, Line 10: receive received
Hello build bot (Jenkins), Sheng-Liang Pan,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45111
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/2
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45111/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/45111/1//COMMIT_MSG@10 PS1, Line 10: receive
received
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 2: Code-Review+1
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 2: Code-Review+1
Hello build bot (Jenkins), Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Sheng-Liang Pan, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45111
to look at the new patch set (#3).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 105 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 3:
(3 comments)
Hey David, what do you think about rebasing this on top of CB:45179 ?
The DPTF changes here could then look like:
register "policies.active" = "{ [0] = {.target=DPTF_CPU, .thresholds={TEMP_PCT(94, 100),}}, [1] = {.target=DPTF_TEMP_SENSOR_2, .thresholds={TEMP_PCT(64, 100), TEMP_PCT(60, 90), TEMP_PCT(56, 80), TEMP_PCT(52, 70), TEMP_PCT(48, 60), TEMP_PCT(44, 50), TEMP_PCT(40, 40),}}}"
register "policies.passive" = "{ [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
register "controls.power_limits" = "{ .pl1 = {.min_power = 12000, .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200,}, .pl2 = {.min_power = 15000, .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}}"
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/voxel/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 17: # Default DPTF Policy for all Volteer boards if not overridden not true here 😊
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 83: ## Charger Performance Control (Control, mA) : register "controls.charger_perf[0]" = "{ 255, 1700 }" : register "controls.charger_perf[1]" = "{ 24, 1500 }" : register "controls.charger_perf[2]" = "{ 16, 1000 }" : register "controls.charger_perf[3]" = "{ 8, 500 }" : : ## Fan Performance Control (Percent, Speed, Noise, Power) : register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" : register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" : register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" : register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" : register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" : register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" : register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" : register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" : register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" : register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }" identical to what is already in the baseboard tree, not required here.
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 101: # Fan options : register "options.fan.fine_grained_control" = "1" : register "options.fan.step_size" = "2" identical to what is already in the baseboard tree, not required here.
Hello build bot (Jenkins), Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Sheng-Liang Pan, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45111
to look at the new patch set (#4).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 84 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/4
David Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 4:
(3 comments)
Thanks
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/voxel/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 17: # Default DPTF Policy for all Volteer boards if not overridden
not true here 😊
Done
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 83: ## Charger Performance Control (Control, mA) : register "controls.charger_perf[0]" = "{ 255, 1700 }" : register "controls.charger_perf[1]" = "{ 24, 1500 }" : register "controls.charger_perf[2]" = "{ 16, 1000 }" : register "controls.charger_perf[3]" = "{ 8, 500 }" : : ## Fan Performance Control (Percent, Speed, Noise, Power) : register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }" : register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }" : register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }" : register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }" : register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }" : register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }" : register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }" : register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }" : register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }" : register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
identical to what is already in the baseboard tree, not required here.
Done
https://review.coreboot.org/c/coreboot/+/45111/3/src/mainboard/google/voltee... PS3, Line 101: # Fan options : register "options.fan.fine_grained_control" = "1" : register "options.fan.step_size" = "2"
identical to what is already in the baseboard tree, not required here.
Done
Hello build bot (Jenkins), Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Sheng-Liang Pan, Peter Ou,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45111
to look at the new patch set (#5).
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 62 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/45111/5
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45111 )
Change subject: mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset ......................................................................
mb/google/volteer/var/voxel: Update DPTF parameters and TCC offset
1. Set tcc offset to 5 degree celsius 2. Apply the DPTF parameters received from the thermal team.
BUG=b:167523658 TEST=build and verify by thermal team
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: I01a6fc5bd959798c8dd423df3907c69c883733e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45111 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 62 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..330d852 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,5 +1,67 @@ chip soc/intel/tigerlake + register "tcc_offset" = "5" # TCC of 95 + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 71, + }" + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_pl1_override = 18, + .tdp_pl2_override = 51, + .tdp_pl4 = 105, + }" + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + ## Active Policy + register "policies.active" = "{ + [0] = {.target = DPTF_CPU, + .thresholds = {TEMP_PCT(94, 100),}}, + [1] = {.target = DPTF_TEMP_SENSOR_2, + .thresholds = {TEMP_PCT(64, 100), + TEMP_PCT(60, 90), + TEMP_PCT(56, 80), + TEMP_PCT(52, 70), + TEMP_PCT(48, 60), + TEMP_PCT(44, 50), + TEMP_PCT(40, 40),}}}" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 54, 6000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}" + + ## Power Limits Control + # 12-18W PL1 in 200mW increments, avg over 28-32s interval + # PL2 is fixed at 51W, avg over 28-32s interval + register "controls.power_limits" = "{ + .pl1 = {.min_power = 12000, + .max_power = 18000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200,}, + .pl2 = {.min_power = 15000, + .max_power = 51000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000,}}" + + device generic 0 on end + end + end # DPTF 0x9A03 device pci 15.0 on chip drivers/i2c/generic register "hid" = ""10EC5682""
-
David Wu (Code Review) -
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)
-
Sheng-Liang Pan (Code Review)
-
Tim Wawrzynczak (Code Review)