Change in coreboot[master]: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Karthik Ramasubramanian, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Martin Roth, Marshall Dawson, Paul Menzel, Karthik Ramasubramanian, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/55987

to look at the new patch set (#3).

Change subject: soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads
......................................................................

soc/amd/common/block/cpu: Cache the uCode to avoid multiple SPI reads

We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.

BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.

Signed-off-by: Raul E Rangel 
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
---
M src/soc/amd/common/block/cpu/update_microcode.c
1 file changed, 36 insertions(+), 13 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/55987/3