Change in coreboot[master]: [UNTESTED] soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted comm...

[Fred Reitberger (Code Review)]

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63305 )

Change subject: [UNTESTED] soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write
......................................................................

[UNTESTED] soc/amd/common/block/spi/fch_spi_ctrl: Fix restricted command write

The SPI_RESTRICTED_CMD register is not a PCI configuration register.  It
is memory mapped from the SPI bar.

Verified against PPR 55570 rev 3.16, PPR 56569 rev 3.03, and PPR 57243
rev 1.50

Change-Id: I7c88aaea9ddac200644bb368be3bd4e9be47fd7b
Signed-off-by: Fred Reitberger 
---
M src/soc/amd/common/block/spi/fch_spi_ctrl.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/63305/1

diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
index b2fe13d..f6cad55 100644
--- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c
+++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c
@@ -270,7 +270,7 @@
    }

/* Final steps to protect region */
-	pci_write_config32(SOC_LPC_DEV, SPI_RESTRICTED_CMD1, reg32);
+	spi_write32(SPI_RESTRICTED_CMD1, reg32);
    reg32 = spi_read32(SPI_CNTRL0);
    reg32 &= ~SPI_ACCESS_MAC_ROM_EN;
    spi_write32(SPI_CNTRL0, reg32);