Change in coreboot[master]: soc/apollolakelake: Make IO decode / enable register configurable

[Sean Rhodes (Code Review)]

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61195 )

Change subject: soc/apollolakelake: Make IO decode / enable register configurable
......................................................................

soc/apollolakelake: Make IO decode / enable register configurable

This allows the one 32bit register to be configured in the
devicetree in the same way that Skylake can be.
i.e. register "lpc_ioe".

Signed-off-by: Sean Rhodes 
Change-Id: I598baca0f31b5350a4e6fdb7b7356fa6fb2d71ed
---
M src/soc/intel/apollolake/bootblock/bootblock.c
M src/soc/intel/apollolake/chip.h
2 files changed, 23 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/61195/1

diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c
index 14e9b11..ee93440 100644
--- a/src/soc/intel/apollolake/bootblock/bootblock.c
+++ b/src/soc/intel/apollolake/bootblock/bootblock.c
@@ -17,6 +17,7 @@
 #include <soc/iomap.h>
 #include <soc/cpu.h>
 #include <soc/gpio.h>
+#include <soc/soc_chip.h>
 #include <soc/systemagent.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
@@ -74,6 +75,9 @@

void bootblock_soc_early_init(void)
 {
+	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
+		LPC_IOE_EC_62_66 | LPC_IOE_LGE_200;
+
    enable_pmcbar();

/* Clear global reset promotion bit */
@@ -82,8 +86,22 @@
    /* Prepare UART for serial console. */
    if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
    	uart_bootblock_init();
-	if (CONFIG(DRIVERS_UART_8250IO))
-		lpc_io_setup_comm_a_b();
+
+	const uint16_t lpc_ioe_enable_mask = LPC_IOE_COMA_EN | LPC_IOE_COMB_EN |
+					     LPC_IOE_LPT_EN | LPC_IOE_FDD_EN |
+					     LPC_IOE_LGE_200 | LPC_IOE_HGE_208 |
+					     LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66 |
+					     LPC_IOE_SUPERIO_2E_2F | LPC_IOE_EC_4E_4F;
+
+	const config_t *config = config_of_soc();
+
+	if (config->lpc_ioe) {
+		io_enables = config->lpc_ioe & lpc_ioe_enable_mask;
+	} else {
+		/* IO Decode Range */
+		if (CONFIG(DRIVERS_UART_8250IO))
+			lpc_io_setup_comm_a_b();
+	}

if (CONFIG(TPM_ON_FAST_SPI))
    	tpm_enable();
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 482b333..922214f 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -106,6 +106,9 @@
    uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */
    uint8_t gpe0_dw3; /* GPE0_127_96 STS/EN */

+	/* LPC fixed enables and ranges */
+	uint32_t lpc_ioe;
+
    /* Configure LPSS S0ix Enable */
    uint8_t lpss_s0ix_enable;