Change in coreboot[master]: mb/google/brya: Add the first FW_CONFIG fields to brya0

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54097 )

Change subject: mb/google/brya: Add the first FW_CONFIG fields to brya0
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mb/google/brya: Add the first FW_CONFIG fields to brya0

1) USB sub-board
2) SD sub-board
3) GSC
4) Keyboard backlight
5) Audio sub-board
6) LTE module

Signed-off-by: Tim Wawrzynczak 
Change-Id: I74ca5ab5366a17e9e1784ec872b9cd77f8663c7f
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/brya0/overridetree.cb
2 files changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/54097/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index a910cc7..1e857c2 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -13,6 +13,8 @@
    select EC_GOOGLE_CHROMEEC_BOARDID
    select EC_GOOGLE_CHROMEEC_ESPI
    select EC_GOOGLE_CHROMEEC_SKUID
+	select FW_CONFIG
+	select FW_CONFIG_SOURCE_CHROMEEC_CBI
    select GOOGLE_SMBIOS_MAINBOARD_VERSION
    select HAVE_ACPI_RESUME
    select HAVE_ACPI_TABLES
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index b5679c8..e601f18 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -1,3 +1,34 @@
+fw_config
+	field DB_USB 0 3
+		option USB_ABSENT		0
+		option USB3_PS8815		1
+	end
+	field DB_SD 4 5
+		option SD_ABSENT		0
+		option SD_GL9755S		1
+	end
+	field GSC 6 6
+		option H1D			0
+		option H1B			1
+	end
+	field KB_BL 7 7
+		option KB_BL_ABSENT		0
+		option KB_BL_PRESENT		1
+	end
+	field AUDIO 8 10
+		option AUDIO_UNKNOWN		0
+		option MAX98357_ALC5682I_I2S	1
+		option MAX98373_ALC5682_SNDW	2
+		option MAX98373_NAU88L25B_I2S	3
+		option ALC1019_NAU88L25B_I2S	4
+	end
+	field DB_LTE 11 12
+		option LTE_ABSENT		0
+		option LTE_USB			1
+		option LTE_PCIE			2
+	end
+end
+
 chip soc/intel/alderlake
    register "SaGv" = "SaGv_Disabled"