[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()

[SH Kim (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Sumeet R Pawnikar.

SH Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email )

Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
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Patch Set 7:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81436/comment/285df4a0_a11fa176 :
PS5, Line 13: override the PL4 value
> Please add me in this bug b/328729536.  […]

The purpose of this code is to override PL1/PL2/PL4 settings for the each board according to thier power/thermal design.

The main reason for this CL was current code cannot set tdp_pl4 value since the pointer variable is incorrect. I corrected it.

About setting tdp_pl1_override and tdp_pl2_override is just my suggestion. In case of "AC only" or "Critical battery" case, we may want to limit PL2/PL4 like this: https://review.coreboot.org/c/coreboot/+/79329.
We override PL1 and PL2 of coreboot DTT setting only. As I know DTT will use DTT policy in OS than coreboot DTT config, then DTT can set to higher value. So I thought PL2 MMIO override doesn't have any effect in this case. (e.g. coreboot DTT PL2: 40W, but OS DTT policy can be PL2: 60W) If I'm misunderstanding about DTT or it's nothing to be worried about, we just can forget this scenario.