Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33522 )
Change subject: src/mb/gigabyte/ga-h61m-s2pv: Correct devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/33522/2/src/mainboard/gigabyte/ga-h61m-s2pv/... File src/mainboard/gigabyte/ga-h61m-s2pv/devicetree.cb:
https://review.coreboot.org/#/c/33522/2/src/mainboard/gigabyte/ga-h61m-s2pv/... PS2, Line 96: irq 0xf1 = 0x40 I don't think these fake `irq` settings work, can you test? For the usual miscellaneous registers 0xf0..0xfe, we have specific hints in the code `PNP_MSC0..PNP_MSCE` but not even the `PNP_MSC1` flag for 0xf1 is set for this LDN.
I think for the global registers it is worth to add `chip.h` settings and write readable init code. Don't know what to do about 0xcb. GPIO settings shouldn't this cryptic, though.
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Nico Huber (Code Review)