[XS] Change in coreboot[main]: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85106?usp=email )

Change subject: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration
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mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration

This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to
accommodate different hardware configurations.

Specifically, GPP_E07 is not connected (NC) on google/fatcat boards with
the Microchip EC AIC. However, it is required for google/fatcat boards
with Nuvoton/ITE AICs.

Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2
Signed-off-by: Subrata Banik 
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85106/1

diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
index 7833fe8..14d38a9 100644
--- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c
+++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c
@@ -210,8 +210,13 @@
    PAD_CFG_GPO(GPP_E03, 1, PLTRST),
    /* GPP_E06:     SECURE_CAM_SW */
    PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+#if CONFIG(BOARD_GOOGLE_FATCAT)
    /* GPP_E07:     Not used */
    PAD_NC(GPP_E07, NONE),
+#else
+	/* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+	PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+#endif
    /* GPP_E08:     Not used */
    PAD_NC(GPP_E08, NONE),
    /* GPP_E09:     USB_RD_FP_CONN_12_OC0_N */