Change in coreboot[master]: soc/intel/alderlake: Add support for UFS controller

[Subrata Banik (Code Review)]

Attention is currently required from: Wonkyu Kim, Kangheui Won, Tim Wawrzynczak, Paul Menzel, Rizwan Qureshi, Angel Pons, Meera Ravindranath, Lean Sheng Tan.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62856 )

Change subject: soc/intel/alderlake: Add support for UFS controller
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Patch Set 2:

(2 comments)

File src/soc/intel/alderlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/62856/comment/601a3283_268e8fe0 
PS2, Line 620: 	/* UFS */
> Hi Meera, I checked the EDS, seems like UFS on both ADL have only 1 port, but 2 lanes? So i presume that the UfsEnable[] is referring to port, not lane?

for sure, it's port not lane.

I would expect FSP to refer at GLK UFS UPD, It might have avoid confusion a lot, just an integer instead array.

src/vendorcode/intel/fsp/fsp2_0//glk/FspsUpd.h:1119:  UINT8                       UfsEnabled;

When you say there is only 1 UFS controller, then for sure, we expect, it's mapped to index 0 or port 0, unless we actually also say it's over port 1 or index 1 mapped.

https://review.coreboot.org/c/coreboot/+/62856/comment/eeb9b94e_8a09595b 
PS2, Line 625: 		s_cfg->UfsEnable[1] = dev->enabled;
I would also explicitly mark UFS UPD index 0 as `0` to make sure it's marked disable

s_cfg->UfsEnable[0] = 0; /* UFS controller 0 is fused disable */
s_cfg->UfsEnable[1] = is_devfn_enabled(PCH_DEVFN_UFS);