Change in coreboot[master]: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29284 )

Change subject: soc/intel/braswell/chip.c: Configure LPSS devices in correct mode
......................................................................

Patch Set 11:

(1 comment)

https://review.coreboot.org/c/coreboot/+/29284/11//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/29284/11//COMMIT_MSG@11 
PS11, Line 11: ACPI mode, functions > 1 are not available on the PCI bus, even pcdEnableXXXXX is set to
Is this actually the case or that function 0 disappears and that w/o a function 0 probing doesn't occur because it's against PCI standard? My recollection was the latter. And below your further comments suggest that as well. I don't think the devices disappear off the bus.