Change in coreboot[master]: soc/intel/cannonlake: Fix xhci ASL

[Vaibhav Shankar (Code Review)]

Vaibhav Shankar has uploaded this change for review. ( https://review.coreboot.org/22389

Change subject: soc/intel/cannonlake: Fix xhci ASL
......................................................................

soc/intel/cannonlake: Fix xhci ASL

During S3 cycling, system entered S3 only once and falied to
enter S3 the second time. The system gets stuck at this point
and we have to do a cold reboot to restore the system.

This patch removes SS clk trunk gating. This helps in continuous
cycling of S3.

TEST=run powerd_dbus_suspend multiple times and check if
the system enters and resumes from S3.

Change-Id: Id459631ea2d32feea4b8f658fd34fa25945f909e
Signed-off-by: Vaibhav Shankar 
---
M src/soc/intel/cannonlake/acpi/xhci.asl
1 file changed, 2 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/22389/1

diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl
index 4c1b08b..f3b300b 100644
--- a/src/soc/intel/cannonlake/acpi/xhci.asl
+++ b/src/soc/intel/cannonlake/acpi/xhci.asl
@@ -94,9 +94,6 @@
    	Offset (0x10),
    	, 16,
    	XMEM, 16,	/* MEM_BASE */
-		Offset (0x50),	/* XHCLKGTEN */
-		, 2,
-		STGE, 1,	/* SS Link Trunk clock gating enable */
    	Offset (0x74),
    	D0D3, 2,	/* POWERSTATE */
    	, 6,
@@ -131,9 +128,8 @@
    		Return
    	}

-		/* Disable d3hot and SS link trunk clock gating */
+		/* Disable d3hot */
    	Store(Zero, ^D3HE)
-		Store(Zero, ^STGE)

/* If device is in D3, set back to D0 */
    	If (LEqual (^D0D3, 3)) {
@@ -171,9 +167,8 @@
    	/* Enable USB2 PHY SUS Well Power Gating in D0/D0i2/D0i3/D3 */
    	Store (3, ^UPSW)

-		/* Enable d3hot and SS link trunk clock gating */
+		/* Enable d3hot */
                 Store(One, ^D3HE)
-                Store(One, ^STGE)

/* Now put device in D3 */
    	Store (3, Local0)