Change in coreboot[master]: amdfwtool: Add a macro to set explicitly second gen for old SOCs

[Bao Zheng (Code Review)]

Attention is currently required from: Zheng Bao.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/63319

to review the following change.

Change subject: amdfwtool: Add a macro to set explicitly second gen for old SOCs
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amdfwtool: Add a macro to set explicitly second gen for old SOCs

It is more reasonable than getting the value from memset.

Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao 
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/amdfwtool.h
2 files changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63319/1

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 80595ddb..bdb18b9 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1383,6 +1383,7 @@
    }
    switch (soc_id) {
    case PLATFORM_STONEYRIDGE:
+		amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
    	amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode;
    	amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed;
    	break;
@@ -1390,6 +1391,7 @@
    case PLATFORM_PICASSO:
    	/* amd_romsig->efs_gen introduced after RAVEN/PICASSO.
    	 * Leave as 0xffffffff for first gen */
+		amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN;
    	amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode;
    	amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed;
    	switch (efs_spi_micron_flag) {
diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h
index a241316..3af4e94 100644
--- a/util/amdfwtool/amdfwtool.h
+++ b/util/amdfwtool/amdfwtool.h
@@ -88,6 +88,7 @@
 } __attribute__((packed));

#define EFS_SECOND_GEN 0
+#define EFS_BEFORE_SECOND_GEN 1

typedef struct _embedded_firmware {
    uint32_t signature; /* 0x55aa55aa */