Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37217 )
Change subject: sb/intel/*: Remove romcc guards ......................................................................
sb/intel/*: Remove romcc guards
These platforms now use a GCC compiled bootblock.
Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h 4 files changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/37217/1
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; };
-#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif
void early_usb_init(const struct southbridge_usb_port *portmap);
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@
#if !defined(__ACPI__)
-#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif
void i82371eb_hard_reset(void);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
-#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif
void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@
void early_usb_init(const struct southbridge_usb_port *portmap);
-#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37217 )
Change subject: sb/intel/*: Remove romcc guards ......................................................................
Patch Set 2: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37217 )
Change subject: sb/intel/*: Remove romcc guards ......................................................................
sb/intel/*: Remove romcc guards
These platforms now use a GCC compiled bootblock.
Change-Id: I9a0139f497fe84860664195ed6584f90daecec16 Signed-off-by: Arthur Heymans arthur@aheymans.xyz Reviewed-on: https://review.coreboot.org/c/coreboot/+/37217 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/ibexpeak/pch.h 4 files changed, 0 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 127fb61..089d458 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -90,10 +90,8 @@ int oc_pin; };
-#ifndef __ROMCC__ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; -#endif
void early_usb_init(const struct southbridge_usb_port *portmap);
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index 77931cb..d35b215 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -19,10 +19,8 @@
#if !defined(__ACPI__)
-#ifndef __ROMCC__ #include <device/device.h> void i82371eb_enable(struct device *dev); -#endif
void i82371eb_hard_reset(void);
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 3d27faa..0516a7a 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -34,10 +34,8 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0
-#ifndef __ROMCC__ #include <device/device.h> void i82801gx_enable(struct device *dev); -#endif
void enable_smbus(void); void i82801gx_lpc_setup(void); diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 9ee76f2..5785ef1 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -89,11 +89,9 @@
void early_usb_init(const struct southbridge_usb_port *portmap);
-#ifndef __ROMCC__ extern const struct southbridge_usb_port mainboard_usb_ports[14]; #include <device/device.h> void pch_enable(struct device *dev); -#endif
#define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1
-
Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)
-
Nico Huber (Code Review)