Patch merged into coreboot/master: 9d5e900 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.

the following patch was just integrated into master:
commit 9d5e9007d6e6d89209bead7f562f3da6350911cf
Author: Edward O'Callaghan 
Date:   Sun Mar 9 17:46:39 2014 +1100

mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.

The platform dependent mainboard.c was incorrectly disabling the
    second clock signal feeding the GPP ports. This results in
    spurious hangs by calling the set_pcie_dereset() SB CIMx callback
    many times. This also stops coreboot from finding the second NIC
    behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
    Signed-off-by: Edward O'Callaghan

See http://review.coreboot.org/5355 for details.

-gerrit