Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32994
Change subject: mb/google/arcada: Disable Heci1 ......................................................................
mb/google/arcada: Disable Heci1
Change-Id: I1ea5326192c95936c39612c425db0289c8c40601 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32994/1
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index c96423c..27b928f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -30,6 +30,7 @@ register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s register "PchPmSlpAMinAssert" = "4" # 2s + register "Heci1Disabled" = "1"
register "speed_shift_enable" = "1" register "s0ix_enable" = "1"
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32994
to look at the new patch set (#3).
Change subject: mb/google/sarien: Disable Heci1 ......................................................................
mb/google/sarien: Disable Heci1
Change-Id: I1ea5326192c95936c39612c425db0289c8c40601 Signed-off-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32994/3
Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32994 )
Change subject: mb/google/sarien: Disable Heci1 ......................................................................
Abandoned
Abandon due to 33194
-
Bora Guvendik (Code Review)