New subject: Change in coreboot[master]: [WIP] mb/acer/m3800: add Acer Aspire M3800 desktop

4 Aug 2020

Michael has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44167 )
Change subject: mb/acer/m3800: add Acer Aspire M3800 desktop
......................................................................
mb/acer/m3800: add Acer Aspire M3800 desktop
Adds a new port for the Aspire M3800 of which I only own the mainboard
named "Acer G43T-AM3" (sticker). In DMI data it is additionally called
Acer EG43M.
The Aspire M5800 model seems to use the same mainboard. The BIOS you can
download from Acer is identical for both.
It is a microATX-sized board with an LGA 775 socket, four DDR3 DIMM
slots, one PCIe x16 slot, one PCIe x1 slot and two PCI slots based on
the Intel G43 chipset.
The port was started by copying mb/intel/dg43gt (not going to lie here)
and adapting things by looking at dumps from the system when running
with the vendor BIOS. Serial console output is possible by soldering to
a point at the corresponding Super IO pin.
The service manual for the board was helpful for setting the correct PCI
IRQ links. It can be found publicly on the internet as the "Acer Aspire
M3800 Service Manual".
Working:
- CPUs from Pentium Dual-Core E2160 to Core2 Quad Q9550 at FSB1333
- At least three DIMM slots (no fourth DIMM at hand) at 1066 MHz
- PS/2 keyboard and mouse
- USB ports (8 internal, 4 external)
- Both PCI ports with various cards (Ethernet, audio, USB, VGA)
- Integrated graphics (libgfxinit)
- HDMI and VGA ports
- boot with PCIe graphics and SeaBIOS
- boot with PCI VGA and SeaBIOS
- Both PCIe ports
- Intel GbE
- All six SATA ports
- Native raminit
- Flashing with flashrom
- Rear audio output
- SeaBIOS to boot slackware64
- SeaBIOS to boot Windows 10 (needs VGA BIOS)
- Temperature readings (including PECI)
- SuperIO EC automatic fan control
- Poweroff
Not working:
- S3 suspend/resume ("RAM INIT FAILURE!" on resume)
- Resource issues with the VGA BIOS of a PCI rv100-based card
- SuperIO voltage reading conversions
Untested:
- The other audio jacks or the front panel header
- On-board Firewire
- EHCI debug
- VBT (was extracted and added, but don't know how to test)
- SuperIO GPIOs
Signed-off-by: Michael Büchler michael.buechler@posteo.net
Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
---
A src/mainboard/acer/Kconfig
A src/mainboard/acer/Kconfig.name
A src/mainboard/acer/m3800/Kconfig
A src/mainboard/acer/m3800/Kconfig.name
A src/mainboard/acer/m3800/Makefile.inc
A src/mainboard/acer/m3800/acpi/ec.asl
A src/mainboard/acer/m3800/acpi/ich10_pci_irqs.asl
A src/mainboard/acer/m3800/acpi/superio.asl
A src/mainboard/acer/m3800/acpi_tables.c
A src/mainboard/acer/m3800/board_info.txt
A src/mainboard/acer/m3800/cmos.default
A src/mainboard/acer/m3800/cmos.layout
A src/mainboard/acer/m3800/cstates.c
A src/mainboard/acer/m3800/data.vbt
A src/mainboard/acer/m3800/devicetree.cb
A src/mainboard/acer/m3800/dsdt.asl
A src/mainboard/acer/m3800/early_init.c
A src/mainboard/acer/m3800/gma-mainboard.ads
A src/mainboard/acer/m3800/gpio.c
A src/mainboard/acer/m3800/hda_verb.c
20 files changed, 634 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/44167/1

diff --git a/src/mainboard/acer/Kconfig b/src/mainboard/acer/Kconfig
new file mode 100644
index 0000000..1c39839
--- /dev/null
+++ b/src/mainboard/acer/Kconfig
@@ -0,0 +1,18 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if VENDOR_ACER
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/acer/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/acer/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Acer"
+
+endif # VENDOR_ACER
diff --git a/src/mainboard/acer/Kconfig.name b/src/mainboard/acer/Kconfig.name
new file mode 100644
index 0000000..bb177f9
--- /dev/null
+++ b/src/mainboard/acer/Kconfig.name
@@ -0,0 +1,2 @@
+config VENDOR_ACER
+	bool "Acer"
diff --git a/src/mainboard/acer/m3800/Kconfig b/src/mainboard/acer/m3800/Kconfig
new file mode 100644
index 0000000..f95e430
--- /dev/null
+++ b/src/mainboard/acer/m3800/Kconfig
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_ACER_M3800
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select CPU_INTEL_SOCKET_LGA775
+	select NORTHBRIDGE_INTEL_X4X
+	select SOUTHBRIDGE_INTEL_I82801JX
+	select SUPERIO_ITE_IT8720F
+	select HAVE_ACPI_TABLES
+	select BOARD_ROMSIZE_KB_2048
+	select PCIEXP_ASPM
+	select PCIEXP_CLK_PM
+	select HAVE_OPTION_TABLE
+	select HAVE_CMOS_DEFAULT
+	select HAVE_ACPI_RESUME
+	select DRIVERS_I2C_CK505
+	select INTEL_GMA_HAVE_VBT
+	select MAINBOARD_HAS_LIBGFXINIT
+	select MAINBOARD_USES_IFD_GBE_REGION
+
+config VGA_BIOS_ID
+	string
+	default "8086,2e22"
+
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xe0000000
+
+config MAINBOARD_DIR
+	string
+	default "acer/m3800"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "M3800"
+
+config MAX_CPUS
+	int
+	default 4
+
+endif # BOARD_ACER_M3800
diff --git a/src/mainboard/acer/m3800/Kconfig.name b/src/mainboard/acer/m3800/Kconfig.name
new file mode 100644
index 0000000..ca6fd53
--- /dev/null
+++ b/src/mainboard/acer/m3800/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ACER_M3800
+	bool "M3800"
diff --git a/src/mainboard/acer/m3800/Makefile.inc b/src/mainboard/acer/m3800/Makefile.inc
new file mode 100644
index 0000000..ede8d87
--- /dev/null
+++ b/src/mainboard/acer/m3800/Makefile.inc
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += cstates.c
+romstage-y += gpio.c
+
+bootblock-y += early_init.c
+romstage-y += early_init.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/acer/m3800/acpi/ec.asl b/src/mainboard/acer/m3800/acpi/ec.asl
new file mode 100644
index 0000000..2997587
--- /dev/null
+++ b/src/mainboard/acer/m3800/acpi/ec.asl
@@ -0,0 +1 @@
+/* dummy */
diff --git a/src/mainboard/acer/m3800/acpi/ich10_pci_irqs.asl b/src/mainboard/acer/m3800/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000..b7588dc
--- /dev/null
+++ b/src/mainboard/acer/m3800/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+	Return (Package() {
+		/* PCI slot */
+		Package() { 0x0001ffff, 0, 0, 0x14},
+		Package() { 0x0001ffff, 1, 0, 0x15},
+		Package() { 0x0001ffff, 2, 0, 0x16},
+		Package() { 0x0001ffff, 3, 0, 0x17},
+
+		Package() { 0x0002ffff, 0, 0, 0x15},
+		Package() { 0x0002ffff, 1, 0, 0x16},
+		Package() { 0x0002ffff, 2, 0, 0x17},
+		Package() { 0x0002ffff, 3, 0, 0x14},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0001ffff, 0, _SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 1, _SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, _SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 3, _SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0002ffff, 0, _SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0002ffff, 1, _SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0002ffff, 2, _SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0002ffff, 3, _SB.PCI0.LPCB.LNKE, 0},
+	})
+}
diff --git a/src/mainboard/acer/m3800/acpi/superio.asl b/src/mainboard/acer/m3800/acpi/superio.asl
new file mode 100644
index 0000000..23fa2df
--- /dev/null
+++ b/src/mainboard/acer/m3800/acpi/superio.asl
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8720F_SHOW_SP1
+#undef IT8720F_SHOW_SP2
+#undef IT8720F_SHOW_EC
+#undef IT8720F_SHOW_KBCK
+#undef IT8720F_SHOW_KBCM
+#undef IT8720F_SHOW_GPIO
+#undef IT8720F_SHOW_CIR
+#define SUPERIO_DEV		SIO0
+#define SUPERIO_PNP_BASE	0x2e
+#define IT8720F_SHOW_SP1	0
+#define IT8720F_SHOW_SP2	0
+#define IT8720F_SHOW_EC		1
+#define IT8720F_SHOW_KBCK	1
+#define IT8720F_SHOW_KBCM	1
+#define IT8720F_SHOW_GPIO	1
+#define IT8720F_SHOW_CIR	0
+#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/acer/m3800/acpi_tables.c b/src/mainboard/acer/m3800/acpi_tables.c
new file mode 100644
index 0000000..1485b67
--- /dev/null
+++ b/src/mainboard/acer/m3800/acpi_tables.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <southbridge/intel/i82801jx/nvs.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+	gnvs->pwrs = 1;	   /* Power state (AC = 1) */
+	gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */
+	gnvs->apic = 1;	   /* Enable APIC */
+	gnvs->mpen = 1;	   /* Enable Multi Processing */
+}
diff --git a/src/mainboard/acer/m3800/board_info.txt b/src/mainboard/acer/m3800/board_info.txt
new file mode 100644
index 0000000..aaf657b
--- /dev/null
+++ b/src/mainboard/acer/m3800/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/acer/m3800/cmos.default b/src/mainboard/acer/m3800/cmos.default
new file mode 100644
index 0000000..706f5dd
--- /dev/null
+++ b/src/mainboard/acer/m3800/cmos.default
@@ -0,0 +1,6 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/acer/m3800/cmos.layout b/src/mainboard/acer/m3800/cmos.layout
new file mode 100644
index 0000000..79bb1b8
--- /dev/null
+++ b/src/mainboard/acer/m3800/cmos.layout
@@ -0,0 +1,97 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+#390          5       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395          4       e       6        debug_level
+
+# coreboot config options: southbridge
+408         1       e       10        sata_mode
+409          2       e       7        power_on_after_fail
+411          1       e       1        nmi
+
+# coreboot config options: cpu
+#424        8       r       0        unused
+
+# coreboot config options: northbridge
+432         4        e      11        gfx_uma_size
+#435        549       r       0        unused
+
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+1024        144       r       0        recv_enable_results
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+10    0     AHCI
+10    1     Compatible
+11    1     4M
+11    2     8M
+11    3     16M
+11    4     32M
+11    5     48M
+11    6     64M
+11    7     128M
+11    8     256M
+11    9     96M
+11    10     160M
+11    11     224M
+11    12     352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/acer/m3800/cstates.c b/src/mainboard/acer/m3800/cstates.c
new file mode 100644
index 0000000..21b18b9
--- /dev/null
+++ b/src/mainboard/acer/m3800/cstates.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+	return 0;
+}
diff --git a/src/mainboard/acer/m3800/data.vbt b/src/mainboard/acer/m3800/data.vbt
new file mode 100644
index 0000000..646adba
--- /dev/null
+++ b/src/mainboard/acer/m3800/data.vbt
Binary files differ
diff --git a/src/mainboard/acer/m3800/devicetree.cb b/src/mainboard/acer/m3800/devicetree.cb
new file mode 100644
index 0000000..f486e5d
--- /dev/null
+++ b/src/mainboard/acer/m3800/devicetree.cb
@@ -0,0 +1,164 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x	# CPU
+			device lapic 0xacac off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		subsystemid 0x8086 0x0028 inherit
+		device pci 0.0 on  end		# Host Bridge
+		device pci 2.0 on  end		# Integrated graphics controller
+		device pci 2.1 on  end		# Integrated graphics controller 2
+		device pci 3.0 off end		# ME
+		device pci 3.1 off end		# ME
+		chip southbridge/intel/i82801jx	# Southbridge
+			register "gpe0_en" = "0x40"
+
+			# Set AHCI mode.
+			register "sata_port_map"	= "0x3f"
+			register "sata_clock_request"	= "0"
+			register "sata_traffic_monitor"	= "0"
+
+			# Enable PCIe ports 0,1 as slots.
+			register "pcie_slot_implemented" = "0x3"
+
+			# "Additional LPC IO decode ranges": used for SuperIO's
+			# Environment Controller on 0xa15/0xa16
+			register "gen1_dec" = "0x00fc0a01"
+
+			device pci 19.0 on  end		# GBE
+			device pci 1a.0 on  end		# USB
+			device pci 1a.1 on  end		# USB
+			device pci 1a.2 on  end		# USB
+			device pci 1a.7 on  end		# USB
+			device pci 1b.0 on  end		# Audio
+			device pci 1c.0 on  end		# PCIe 1
+			device pci 1c.1 on  end		# PCIe 2
+			device pci 1c.2 off end		# PCIe 3
+			device pci 1c.3 off end		# PCIe 4
+			device pci 1c.4 off end		# PCIe 5
+			device pci 1c.5 off end		# PCIe 6
+			device pci 1d.0 on  end		# USB
+			device pci 1d.1 on  end		# USB
+			device pci 1d.2 on  end		# USB
+			device pci 1d.7 on  end		# USB
+			device pci 1e.0 on  end		# PCI bridge
+			device pci 1f.0 on		# LPC bridge
+				chip superio/ite/it8720f		# Super I/O
+					register "ec.smbus_en"		= "1"
+					register "ec.smbus_24mhz"	= "1"
+					register "TMPIN1.mode"		= "THERMAL_DIODE"
+					register "TMPIN2.mode"		= "THERMAL_RESISTOR"
+					register "TMPIN3.mode"		= "THERMAL_PECI"
+					register "TMPIN3.offset"	= "100"
+					register "TMPIN3.min"		= "0"
+					register "TMPIN3.max"		= "100"
+
+					register "FAN1.mode" = "FAN_SMART_AUTOMATIC"	# CPU fan
+					register "FAN1.smart.tmpin"	= "3"
+					register "FAN1.smart.tmp_off"	= "0"
+					register "FAN1.smart.tmp_start"	= "50"
+					register "FAN1.smart.tmp_full"	= "90"
+					register "FAN1.smart.tmp_delta"	= "3"
+					register "FAN1.smart.full_lmt"	= "1"
+					register "FAN1.smart.smoothing"	= "0"
+					register "FAN1.smart.pwm_start"	= "30"
+					register "FAN1.smart.slope"	= "0x0d"
+					register "FAN2.mode" = "FAN_SMART_AUTOMATIC"	# System fan
+					register "FAN2.smart.tmpin"	= "2"
+					register "FAN2.smart.tmp_off"	= "0"
+					register "FAN2.smart.tmp_start"	= "40"
+					register "FAN2.smart.tmp_full"	= "90"
+					register "FAN2.smart.tmp_delta"	= "2"
+					register "FAN2.smart.full_lmt"	= "0"
+					register "FAN2.smart.smoothing"	= "0"
+					register "FAN2.smart.pwm_start"	= "48"
+					register "FAN2.smart.slope"	= "0x20"
+					register "FAN3.mode" = "FAN_MODE_OFF"		# Not connected
+
+					register "ec.vin_mask" = "VIN_ALL"
+
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 off end		# COM 1
+					device pnp 2e.2 off end		# COM 2
+					device pnp 2e.3 off end		# Parallel port
+					device pnp 2e.4 on		# Environment controller
+						io 0x60 = 0xa10
+						io 0x62 = 0xa00
+						irq 0x70 = 0x00
+						irq 0xf0 = 0x00
+						irq 0xf1 = 0x00
+						irq 0xf2 = 0x00
+						irq 0xf3 = 0x00
+						irq 0xf4 = 0x60
+						irq 0xf5 = 0x00
+						irq 0xf6 = 0x00
+					end
+					device pnp 2e.5 on		# Keyboard
+						io 0x60  = 0x060
+						irq 0x70 = 0x1
+						io 0x62  = 0x064
+						irq 0xf0 = 0x00
+					end
+					device pnp 2e.6 on		# Mouse
+						irq 0x70 = 0x0c
+						irq 0xf0 = 0x00
+					end
+					device pnp 2e.7 on  		# GPIO
+						io 0x60 = 0x000
+						io 0x62 = 0xa20
+						io 0x64 = 0xa30
+						irq 0xbb = 0x01		# GPIO Set 4 Pull-Up
+						irq 0xc0 = 0x01		# Simple IO Set 1
+						irq 0xc1 = 0x0c		# Simple IO Set 2
+						irq 0xc2 = 0x70		# Simple IO Set 3
+						irq 0xc3 = 0x00		# Simple IO Set 4
+						irq 0xc8 = 0x01		# Simple IO Set 1 Output
+						irq 0xc9 = 0x0c		# Simple IO Set 2 Output
+						irq 0xca = 0x00		# Simple IO Set 3 Output
+						irq 0xcb = 0x00		# Simple IO Set 4 Output
+						irq 0xf0 = 0x00
+						irq 0xf1 = 0x00
+						irq 0xf2 = 0x00
+						irq 0xf3 = 0x00
+						irq 0xf4 = 0x00
+						irq 0xf5 = 0x00
+						irq 0xf6 = 0x00
+						irq 0xf7 = 0x00
+						irq 0xf8 = 0x12
+						irq 0xf9 = 0x02
+						irq 0xfa = 0x13
+						irq 0xfb = 0x02
+						#irq 0xfc = 0xef	# VID Input
+						irq 0xfd = 0x00
+						irq 0xfe = 0x00
+					end
+					device pnp 2e.a off end		# CIR
+				end
+			end
+			device pci 1f.1 on  end		# PATA/IDE
+			device pci 1f.2 on  end		# SATA (IDE: port 0-3, AHCI/RAID: 0-5)
+			device pci 1f.3 on  		# SMBus
+				chip drivers/i2c/ck505	# IDT CV194
+					register "mask" = "{ 0xff, 0xff, 0xff, 0x00,
+							     0xff, 0x00, 0x00, 0x00,
+							     0x00, 0xff, 0xff, 0xff,
+							     0x00, 0xff }"
+					register "regs" = "{ 0x57, 0xd9, 0xfe, 0xff,
+							     0xff, 0x00, 0x00, 0x00,
+							     0x00, 0x24, 0x7d, 0x96,
+							     0x00, 0x9d }"
+					device i2c 69 on end
+				end
+			end
+			device pci 1f.4 off end
+			device pci 1f.5 off end		# SATA 2 (for port 4-5 in IDE mode)
+			device pci 1f.6 off end		# Thermal Subsystem
+		end
+	end
+end
diff --git a/src/mainboard/acer/m3800/dsdt.asl b/src/mainboard/acer/m3800/dsdt.asl
new file mode 100644
index 0000000..de548d1
--- /dev/null
+++ b/src/mainboard/acer/m3800/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20090419	// OEM revision
+)
+{
+	// global NVS and variables
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/i82801jx/acpi/globalnvs.asl>
+
+	Scope (_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/x4x/acpi/x4x.asl>
+			#include <southbridge/intel/i82801jx/acpi/ich10.asl>
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		}
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/acer/m3800/early_init.c b/src/mainboard/acer/m3800/early_init.c
new file mode 100644
index 0000000..7e14c71
--- /dev/null
+++ b/src/mainboard/acer/m3800/early_init.c
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <southbridge/intel/i82801jx/i82801jx.h>
+#include <northbridge/intel/x4x/x4x.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	RCBA32(0x3414) &= ~BUC_LAND; // BUC := Backed Up Control -> LAN is enabled
+}
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+	spd_map[0] = 0x50;
+	spd_map[1] = 0x51;
+	spd_map[2] = 0x52;
+	spd_map[3] = 0x53;
+}
diff --git a/src/mainboard/acer/m3800/gma-mainboard.ads b/src/mainboard/acer/m3800/gma-mainboard.ads
new file mode 100644
index 0000000..c9e4326
--- /dev/null
+++ b/src/mainboard/acer/m3800/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/acer/m3800/gpio.c b/src/mainboard/acer/m3800/gpio.c
new file mode 100644
index 0000000..16ef85d
--- /dev/null
+++ b/src/mainboard/acer/m3800/gpio.c
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_GPIO,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio9 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_OUTPUT,
+	.gpio20 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_OUTPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio9  = GPIO_LEVEL_HIGH,
+	.gpio18 = GPIO_LEVEL_HIGH,
+	.gpio20 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio6  = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+	.gpio18 = GPIO_BLINK,
+
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32  = GPIO_MODE_GPIO,
+	.gpio33  = GPIO_MODE_GPIO,
+	.gpio34  = GPIO_MODE_GPIO,
+	.gpio35  = GPIO_MODE_NATIVE,
+	.gpio36  = GPIO_MODE_NATIVE,
+	.gpio37  = GPIO_MODE_NATIVE,
+	.gpio38  = GPIO_MODE_NATIVE,
+	.gpio39  = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_HIGH,
+	.gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = { };
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = { };
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = { };
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+	},
+
+};
diff --git a/src/mainboard/acer/m3800/hda_verb.c b/src/mainboard/acer/m3800/hda_verb.c
new file mode 100644
index 0000000..32a9b25
--- /dev/null
+++ b/src/mainboard/acer/m3800/hda_verb.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0888,
+	0x1025024c,	// Subsystem ID
+	14,	// Number of entries
+
+	/* Pin Widget Verb Table */
+
+	AZALIA_PIN_CFG(0, 0x11, 0x014b7140),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x01012014),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19850),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19851),
+	AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1b, 0x0221401f),
+	AZALIA_PIN_CFG(0, 0x1c, 0x0181305f),
+	AZALIA_PIN_CFG(0, 0x1d, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1e, 0x18567130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	/* HDMI */
+	0x80862803,
+	0x80860101,
+	1,
+
+	AZALIA_PIN_CFG(0, 0x03, 0x18560010)
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs);
+const u32 cim_verb_data_size = ARRAY_SIZE(cim_verb_data);
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I846cf5f4f1ef27fc644676a4c6f7a333e061f6cf
Gerrit-Change-Number: 44167
Gerrit-PatchSet: 1
Gerrit-Owner: Michael michael.buechler@posteo.net
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-MessageType: newchange



    

Change in coreboot[master]: mb/acer/m3800: add Acer Aspire M3800 desktop