Change in ...coreboot[master]: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate
HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33688
Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ......................................................................
soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/spi.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33688/1
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e734..b797507 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,10 +21,10 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <stdlib.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/dimm_spd.h> #include <amdblocks/car.h> +#include <stddef.h>
#include "chip.h"
diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a2..2089576 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,7 +25,7 @@ #include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <stdlib.h> +#include <stddef.h> #include <timer.h>
union cavium_spi_cfg {
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33688
to look at the new patch set (#4).
Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ......................................................................
soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate
Also, including <types.h>, is supposed to provide stdint and stddef.
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/cavium/cn81xx/spi.c 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33688/4
HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33688 )
Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ......................................................................
Abandoned
see 3202
HAOUAS Elyes has restored this change. ( https://review.coreboot.org/c/coreboot/+/33688 )
Change subject: soc/{amd,cavium}: Use 'include <stdlib.h>' when appropriate ......................................................................
Restored
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33688
to look at the new patch set (#5).
Change subject: soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h> ......................................................................
soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/sm.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/sm.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/cavium/cn81xx/spi.c M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/mediatek/mt8183/ddp.c M src/soc/sifive/fu540/clock.c 13 files changed, 0 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33688/5
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33688 )
Change subject: soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h> ......................................................................
Patch Set 9: Code-Review+2
Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/33688 )
Change subject: soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h> ......................................................................
soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>
Change-Id: I83322e246fe81b97188be17a3fdda16d36df0678 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/33688 Reviewed-by: Kyösti Mälkki kyosti.malkki@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/northbridge.c M src/soc/amd/picasso/sm.c M src/soc/amd/stoneyridge/BiosCallOuts.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/sm.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/cavium/cn81xx/spi.c M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/spi.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/mediatek/mt8183/ddp.c M src/soc/sifive/fu540/clock.c 13 files changed, 0 insertions(+), 13 deletions(-)
Approvals: build bot (Jenkins): Verified Kyösti Mälkki: Looks good to me, approved
diff --git a/src/soc/amd/picasso/northbridge.c b/src/soc/amd/picasso/northbridge.c index 4a1493c..282f962 100644 --- a/src/soc/amd/picasso/northbridge.c +++ b/src/soc/amd/picasso/northbridge.c @@ -33,7 +33,6 @@ #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <arch/bert_storage.h>
diff --git a/src/soc/amd/picasso/sm.c b/src/soc/amd/picasso/sm.c index 803e628..438909d 100644 --- a/src/soc/amd/picasso/sm.c +++ b/src/soc/amd/picasso/sm.c @@ -20,7 +20,6 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> #include <soc/southbridge.h> #include <soc/smbus.h>
diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index c55e734..2ee9278 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> -#include <stdlib.h> #include <amdblocks/agesawrapper.h> #include <amdblocks/dimm_spd.h> #include <amdblocks/car.h> diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index c98d0a9..cd78ff8 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -36,7 +36,6 @@ #include <soc/pci_devs.h> #include <soc/iomap.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <arch/bert_storage.h>
diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index fbcddfa..2dba0d7 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -19,7 +19,6 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> #include <soc/southbridge.h> #include <soc/smbus.h>
diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index a39bf4f..284608c 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h>
void *cbmem_top_chipset(void) diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index 2ba25a2..6a5abb1 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -25,7 +25,6 @@ #include <soc/clock.h> #include <spi-generic.h> #include <spi_flash.h> -#include <stdlib.h> #include <timer.h>
union cavium_spi_cfg { diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 8f1f0e6..494f470 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -15,7 +15,6 @@
#include <device/mmio.h> #include <edid.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 9271d6e..dbbc14d 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <endian.h> #include <gpio.h> -#include <stdlib.h> #include <soc/pll.h> #include <soc/spi.h> #include <timer.h> diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 555bfe9..0a57565 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -15,7 +15,6 @@
#include <device/mmio.h> #include <edid.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index ec08334..8a6e13a 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -16,7 +16,6 @@ #define SOC_MEDIATEK_MT8173_GPIO_H
#include <stdint.h> -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/gpio_common.h>
diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 50d6caf..a54b134 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -15,7 +15,6 @@
#include <device/mmio.h> #include <edid.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index ef6221b..a15e639 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -17,7 +17,6 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> -#include <stdlib.h> #include <stdint.h>
// 33.33 Mhz after reset
-
HAOUAS Elyes (Code Review) -
Kyösti Mälkki (Code Review)