[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15

[Subrata Banik (Code Review)]

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N.

Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email )

Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
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Patch Set 2:

(1 comment)

Patchset:

PS1:
> Document #813032 Panther Lake H I/O RegistersLink Capabilities (LCAP) – Offset 4c  does not provide much information on the encoding of the port number field (see extract below).
> > **Port Number (PN)**
> > Indicates the port number for the root port. This value is different for each implemented port:
> > Port # Value of PN field
> > 1 01h
> > 2 02h
> > 3 03h
> >
> > X 0Xh
> >
> > **Note**: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly.
>
> The final note provides a clue to why it may start with a shift. I determined the value of 0x15 through empirical experiments and verified its consistency across different Panther Lake SKUs. I could not find the specification of the TBT Link Capabilities register for Meteor Lake, but according to [81841 soc/intel/mtl: Fixed TBT PCIe devtree remapping](https://review.coreboot.org/c/coreboot/+/81841), port numbers start at 0x10 on Meteor Lake.
>
> I added some information to the commit message.
>
> The fact that we used a non-specified value on Meteor Lake, in my opinion, is an endorsement to submit this CL. However, I would like to know if there is a way to determine this value through a hardware specification and, in particular, for the following SoC generations.

document 815002, Table 8

```
USB Type-C Subsystem PCIe Root Port #21
```

can you please add this notes in the comment section ?