Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/27450
Change subject: Coverity: Fix CID1393974 ......................................................................
Coverity: Fix CID1393974
Fix OVERFLOW_BEFORE_WIDEN.
Change-Id: I39caea8a248d2f1debfca307f6fb7a2fe3e431b1 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/cavium/cn81xx/gpio.c 1 file changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/27450/1
diff --git a/src/soc/cavium/cn81xx/gpio.c b/src/soc/cavium/cn81xx/gpio.c index 340ac1b..84e36d1 100644 --- a/src/soc/cavium/cn81xx/gpio.c +++ b/src/soc/cavium/cn81xx/gpio.c @@ -103,9 +103,9 @@ printk(BIOS_SPEW, "GPIO(%u): level: %u\n", gpio, !!value);
if (value) - write64(®s->tx_set, 1 << gpio); + write64(®s->tx_set, 1ULL << gpio); else - write64(®s->tx_clr, 1 << gpio); + write64(®s->tx_clr, 1ULL << gpio); }
/* Set GPIO direction to OUTPUT with level */ @@ -153,9 +153,10 @@ return 0;
const u64 reg = read64(®s->rx_dat); - printk(BIOS_SPEW, "GPIO(%u): input: %u\n", gpio, !!(reg & (1 << gpio))); + printk(BIOS_SPEW, "GPIO(%u): input: %u\n", gpio, + !!(reg & (1ULL << gpio)));
- return !!(reg & (1 << gpio)); + return !!(reg & (1ULL << gpio)); }
/* Read GPIO STRAP level sampled at cold boot */ @@ -167,9 +168,10 @@ return 0;
const u64 reg = read64(®s->strap); - printk(BIOS_SPEW, "GPIO(%u): strap: %u\n", gpio, !!(reg & (1 << gpio))); + printk(BIOS_SPEW, "GPIO(%u): strap: %u\n", gpio, + !!(reg & (1ULL << gpio)));
- return !!(reg & (1 << gpio)); + return !!(reg & (1ULL << gpio)); }
/* FIXME: Parse devicetree ? */