Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
Enable PCI device 14.2 to align with kernel
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/1
diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index b7aa11d..7236547 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -304,7 +304,7 @@ end end # USB xHCI device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 off end # PMC SRAM + device pci 14.2 on end # PMC SRAM chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/1//COMMIT_MSG@10 PS1, Line 10: Can you please mention the TEST information?
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#2).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
Enable PCI device 14.2 to align with kernel
TEST: Build and boot dedede to kernel and check device 14.2 is on
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/2
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#3).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
Enable PCI device 14.2 to align with kernel
TEST: Build and boot dedede to kernel and check device 14.2 is listed lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/3
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#4).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
Enable PCI device 14.2 to align with kernel
TEST: Build and boot dedede to kernel and check device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/4
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#5).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
Enable PCI device 14.2 to align with kernel
TEST: Build and boot dedede to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/5
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/1//COMMIT_MSG@10 PS1, Line 10:
Can you please mention the TEST information?
Done
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 5: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG@11 PS5, Line 11: TEST: Nit: "TEST: " -> "TEST=" Also please specify which dedede board being used.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG@9 PS5, Line 9: Enable PCI device 14.2 to align with kernel align with kernel in what sense? The commit message doesn't really capture the motivation behind the change.
Hello build bot (Jenkins), Maulik V Vaghela, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#6).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
According to Jasperlake EDS Vol 1, 14.2 is a PMC SRAM device. This is being controlled by PMC and the kernel's PCI enumeration logic detects this device and puts it as part of device list. Switching it on in coreboot to align with the same.
TEST=Build and boot drawlat to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/6
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG@9 PS5, Line 9: Enable PCI device 14.2 to align with kernel
align with kernel in what sense? The commit message doesn't really capture the motivation behind the […]
Updated the same. Please check.
https://review.coreboot.org/c/coreboot/+/46550/5//COMMIT_MSG@11 PS5, Line 11: TEST:
Nit: "TEST: " -> "TEST=" […]
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG@14 PS6, Line 14: check if device 14.2 is listed : in lspci. Is this device getting used in the kernel for any purpose? Just curious to understand how this is utilized in the kernel.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 6: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/6/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46550/6/src/mainboard/google/dedede... PS6, Line 307: end nit: add an extra space before the `end` so that it aligns with the other lines
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 6:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG@14 PS6, Line 14: check if device 14.2 is listed : in lspci.
Is this device getting used in the kernel for any purpose? Just curious to understand how this is ut […]
It is used for communication with PMC but we don't see binding to any kernel driver. Will try to get more info on this.
https://review.coreboot.org/c/coreboot/+/46550/6/src/mainboard/google/dedede... File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/46550/6/src/mainboard/google/dedede... PS6, Line 307: end
nit: add an extra space before the `end` so that it aligns with the other lines
Done
Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Angel Pons, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#7).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
According to Jasperlake EDS Vol 1, 14.2 is a PMC SRAM device. This is being controlled by PMC and the kernel's PCI enumeration logic detects this device and puts it as part of device list. Switching it on in coreboot to align with the same.
TEST=Build and boot drawlat to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/7
Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Maulik V Vaghela, Angel Pons, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#8).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
According to Jasperlake EDS Vol 1, 14.2 is a PMC SRAM device. This is being controlled by PMC and the kernel's PCI enumeration logic detects this device and puts it as part of device list. Switching it on in coreboot to align with the same.
TEST=Build and boot drawlat to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/8
Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Maulik V Vaghela, Angel Pons, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#9).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
According to Jasperlake EDS Vol 1, 14.2 is a PMC SRAM device. This is being controlled by PMC and the kernel's PCI enumeration logic detects this device and puts it as part of device list. Switching it on in coreboot to align with the same.
TEST=Build and boot drawlat to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/9
Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Maulik V Vaghela, Angel Pons, Aamir Bohra, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46550
to look at the new patch set (#10).
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
mb/google/dedede: Enable PCI device 14.2
According to Jasperlake EDS Vol 1, 14.2 is a PMC SRAM device. This is being controlled by PMC and the kernel's PCI enumeration logic detects this device and puts it as part of device list. Switching it on in coreboot to align with the same.
TEST=Build and boot drawlat to kernel and check if device 14.2 is listed in lspci.
Signed-off-by: Meera Ravindranath meera.ravindranath@intel.com Change-Id: I3eb32218041263f0abef8b9dd4c52efb17289fd7 --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/46550/10
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG@14 PS6, Line 14: check if device 14.2 is listed : in lspci.
It is used for communication with PMC but we don't see binding to any kernel driver. […]
Done
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 10: Code-Review+2
Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 10: Code-Review+2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46550 )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46550/6//COMMIT_MSG@14 PS6, Line 14: check if device 14.2 is listed : in lspci.
Done
Did you get more info on this?
Martin L Roth has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/46550?usp=email )
Change subject: mb/google/dedede: Enable PCI device 14.2 ......................................................................
Abandoned
This patch has not been touched in over 12 months. Anyone who wants to take over work on this patch, please feel free to restore it and do any work needed to get it merged. If you create a new patch based on this work, please credit the original author.
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Angel Pons (Code Review) -
Furquan Shaikh (Code Review)
-
Karthik Ramasubramanian (Code Review)
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Martin L Roth (Code Review)
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Maulik V Vaghela (Code Review)
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Meera Ravindranath (Code Review)
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Subrata Banik (Code Review)