Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40825 )
Change subject: soc/amd/picasso: Add support for em100 ......................................................................
soc/amd/picasso: Add support for em100
This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz.
BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/southbridge.c 2 files changed, 17 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40825/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 3113b27..99e5e59 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -21,6 +21,7 @@ select GENERIC_GPIO_LIB select IOAPIC select HAVE_USBDEBUG_OPTIONS + select HAVE_EM100_SUPPORT select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI select TSC_SYNC_LFENCE diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 1aa7b07..d37f143 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -236,13 +236,27 @@ write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); }
-static void sb_spi_config_modes(void) +static void sb_spi_config_mb_modes(void) { const struct soc_amd_picasso_config *cfg = config_of_soc();
+ sb_read_mode(cfg->spi_read_mode); sb_set_spi100(cfg->spi_normal_speed, cfg->spi_fast_speed, cfg->spi_altio_speed, cfg->spi_tpm_speed); - sb_read_mode(cfg->spi_read_mode); +} + +static void sb_spi_config_em100_modes(void) +{ + sb_read_mode(SPI_READ_MODE_NORMAL33M); + sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +static void sb_spi_config_modes(void) +{ + if (CONFIG(EM100)) + sb_spi_config_em100_modes(); + else + sb_spi_config_mb_modes(); }
static void sb_spi_init(void)
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40825
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Add support for em100 ......................................................................
soc/amd/picasso: Add support for em100
This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz.
BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/southbridge.c 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40825/2
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40825 )
Change subject: soc/amd/picasso: Add support for em100 ......................................................................
Patch Set 4: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40825 )
Change subject: soc/amd/picasso: Add support for em100 ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40825 )
Change subject: soc/amd/picasso: Add support for em100 ......................................................................
soc/amd/picasso: Add support for em100
This change enables support for em100 for Picasso platform. Since em100 requires lower SPI speed, this change configures speed in all modes as 16MHz.
BUG=b:147758054,b:153675510 BRANCH=trembyle-bringup TEST=Verified that em100 works fine on trembyle.
Signed-off-by: Furquan Shaikh furquan@google.com Change-Id: Ib5ea1fe094fda9b8dba63e94b37e61791629564f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40825 Reviewed-by: Raul Rangel rrangel@chromium.org Reviewed-by: Aaron Durbin adurbin@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/southbridge.c 2 files changed, 16 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fa053f9..5996cc6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -21,6 +21,7 @@ select DRIVERS_I2C_DESIGNWARE select GENERIC_GPIO_LIB select IOAPIC + select HAVE_EM100_SUPPORT select HAVE_USBDEBUG_OPTIONS select TSC_MONOTONIC_TIMER select SOC_AMD_COMMON_BLOCK_SPI diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 4f25802..d37f143 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -236,7 +236,7 @@ write32((void *)(base + SPI_CNTRL0), val | SPI_READ_MODE(mode)); }
-static void sb_spi_config_modes(void) +static void sb_spi_config_mb_modes(void) { const struct soc_amd_picasso_config *cfg = config_of_soc();
@@ -245,6 +245,20 @@ cfg->spi_tpm_speed); }
+static void sb_spi_config_em100_modes(void) +{ + sb_read_mode(SPI_READ_MODE_NORMAL33M); + sb_set_spi100(SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M, SPI_SPEED_16M); +} + +static void sb_spi_config_modes(void) +{ + if (CONFIG(EM100)) + sb_spi_config_em100_modes(); + else + sb_spi_config_mb_modes(); +} + static void sb_spi_init(void) { lpc_enable_spi_prefetch();
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
-
Raul Rangel (Code Review)