[S] Change in coreboot[main]: soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84906?usp=email )

(

11 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling
......................................................................

soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling

Extend the 'psp_smi_spi_rpmc_inc_mc' and 'psp_smi_spi_rpmc_req_mc'
function stubs that now implement the actual functionality by calling
'spi_flash_rpmc_increment' and 'spi_flash_rpmc_request' after doing some
sanity checks.

TEST=When selecting both 'SOC_AMD_COMMON_BLOCK_PSP_RPMC' and
'SOC_AMD_COMMON_BLOCK_PSP_SMI' Kconfig options on a board with an RPMC-
capable SPI flash, the PSP SMI handler can successfully service not only
the already working SPI flash write command, but also the increment
monotonic counter RPMC command:

[NOTE ]  coreboot-[...] x86_32 smm starting (log level: 8)...

[SPEW ]  SMI# #0
[SPEW ]  PSP: SPI write request
[DEBUG]  FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ]  PSP: SPI write 0x400 bytes at 0x0

[NOTE ]  coreboot-[...] x86_32 smm starting (log level: 8)...

[SPEW ]  SMI# #0
[SPEW ]  PSP: SPI write request
[DEBUG]  FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ]  PSP: SPI write 0x400 bytes at 0x400

[NOTE ]  coreboot-[...] x86_32 smm starting (log level: 8)...

[SPEW ]  SMI# #8
[SPEW ]  PSP: SPI write request
[DEBUG]  FMAP: area PSP_NVRAM found @ f20000 (131072 bytes)
[SPEW ]  PSP: SPI write 0x310 bytes at 0x800

[NOTE ]  coreboot-[...] x86_32 smm starting (log level: 8)...

[SPEW ]  SMI# #1
[SPEW ]  PSP: SPI write request
[DEBUG]  FMAP: area PSP_RPMC_NVRAM found @ f40000 (262144 bytes)
[SPEW ]  PSP: SPI write 0x70 bytes at 0x100

[NOTE ]  coreboot-[...] x86_32 smm starting (log level: 8)...

[SPEW ]  SMI# #0
[SPEW ]  PSP: SPI RPMC increment monotonic counter request

This requires the PSP_RPMC_NVRAM FMAP section to have the correct size
which in case of Renoir is 256 kByte. Having this large enough size also
makes the PSP report that the PSP RPMC NVRAM is healthy which wasn't the
case in previous tests when the region was too small.

Change-Id: I20e4f60d4e35d33e560fc43212b320e817e13004
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84906
Reviewed-by: Matt DeVillier 
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/common/block/psp/Kconfig
M src/soc/amd/common/block/psp/psp_smi_flash.c
2 files changed, 41 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved
  Matt DeVillier: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig
index 3ae5e43..07ee0fa 100644
--- a/src/soc/amd/common/block/psp/Kconfig
+++ b/src/soc/amd/common/block/psp/Kconfig
@@ -34,6 +34,7 @@
 config SOC_AMD_COMMON_BLOCK_PSP_RPMC
    bool
    depends on SOC_AMD_COMMON_BLOCK_PSP_GEN2
+	select SPI_FLASH_RPMC
    help
      Select this option in the SoC's Kconfig to include the support for
      the replay-protected monotonic counter (RPMC) feature.
diff --git a/src/soc/amd/common/block/psp/psp_smi_flash.c b/src/soc/amd/common/block/psp/psp_smi_flash.c
index abddcdf..a32ba21 100644
--- a/src/soc/amd/common/block/psp/psp_smi_flash.c
+++ b/src/soc/amd/common/block/psp/psp_smi_flash.c
@@ -281,14 +281,52 @@

enum mbox_p2c_status psp_smi_spi_rpmc_inc_mc(struct mbox_default_buffer *buffer)
 {
+	struct mbox_psp_cmd_spi_rpmc_inc_mc *const cmd_buf =
+		(struct mbox_psp_cmd_spi_rpmc_inc_mc *)buffer;
+	const struct spi_flash *flash;
+
    printk(BIOS_SPEW, "PSP: SPI RPMC increment monotonic counter request\n");

-	return MBOX_PSP_UNSUPPORTED;
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_RPMC))
+		return MBOX_PSP_UNSUPPORTED;
+
+	if (spi_controller_busy()) {
+		return MBOX_PSP_SPI_BUSY;
+	}
+
+	if (get_flash_device(&flash) != MBOX_PSP_SUCCESS)
+		return MBOX_PSP_COMMAND_PROCESS_ERROR;
+
+	if (spi_flash_rpmc_increment(flash, cmd_buf->req.counter_address,
+				     cmd_buf->req.counter_data, cmd_buf->req.signature)
+			!= CB_SUCCESS)
+		return MBOX_PSP_COMMAND_PROCESS_ERROR;
+
+	return MBOX_PSP_SUCCESS;
 }

enum mbox_p2c_status psp_smi_spi_rpmc_req_mc(struct mbox_default_buffer *buffer)
 {
+	struct mbox_psp_cmd_spi_rpmc_req_mc *const cmd_buf =
+		(struct mbox_psp_cmd_spi_rpmc_req_mc *)buffer;
+	const struct spi_flash *flash;
+
    printk(BIOS_SPEW, "PSP: SPI RPMC request monotonic counter request\n");

-	return MBOX_PSP_UNSUPPORTED;
+	if (!CONFIG(SOC_AMD_COMMON_BLOCK_PSP_RPMC))
+		return MBOX_PSP_UNSUPPORTED;
+
+	if (spi_controller_busy()) {
+		return MBOX_PSP_SPI_BUSY;
+	}
+
+	if (get_flash_device(&flash) != MBOX_PSP_SUCCESS)
+		return MBOX_PSP_COMMAND_PROCESS_ERROR;
+
+	if (spi_flash_rpmc_request(flash, cmd_buf->req.counter_address, cmd_buf->req.tag,
+				   cmd_buf->req.signature, cmd_buf->req.output_counter_data,
+				   cmd_buf->req.output_signature) != CB_SUCCESS)
+		return MBOX_PSP_COMMAND_PROCESS_ERROR;
+
+	return MBOX_PSP_SUCCESS;
 }