Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/18576 )
Change subject: soc/pci_devs.h: Use consistent naming in soc/pci_devs.h ......................................................................
soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
This patch to make common PCI device name between APL and SKL.
Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Signed-off-by: Barnali Sarkar barnali.sarkar@intel.com Signed-off-by: Subrata Banik subrata.banik@intel.com Reviewed-on: https://review.coreboot.org/18576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cse.c M src/soc/intel/apollolake/flash_ctrlr.c M src/soc/intel/apollolake/graphics.c M src/soc/intel/apollolake/heci.c M src/soc/intel/apollolake/include/soc/i2c.h M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/apollolake/lpc_lib.c M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/p2sb.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/apollolake/uart.c M src/soc/intel/apollolake/uart_early.c M src/soc/intel/apollolake/xdci.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/me.c 24 files changed, 232 insertions(+), 197 deletions(-)
Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7c3f313..9f57206 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -152,7 +152,7 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) { struct soc_intel_apollolake_config *cfg; - struct device *dev = NB_DEV_ROOT; + struct device *dev = SA_DEV_ROOT;
/* Clear out GNVS. */ memset(gnvs, 0, sizeof(*gnvs)); diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cdf3acf..ed4530c 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -51,7 +51,7 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { - device_t dev = NB_DEV_ROOT; + device_t dev = SA_DEV_ROOT;
/* Set PCI Express BAR */ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); @@ -62,7 +62,7 @@ */ pci_write_config32(dev, TSEG, 0);
- dev = P2SB_DEV; + dev = PCH_DEV_P2SB; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */ pci_write_config32(dev, PCI_BASE_ADDRESS_0, CONFIG_IOSF_BASE_ADDRESS); pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); @@ -70,7 +70,7 @@ PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Decode the ACPI I/O port range for early firmware verification.*/ - dev = PMC_DEV; + dev = PCH_DEV_PMC; pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MASTER); @@ -111,7 +111,7 @@ */ static void enable_spibar(void) { - device_t dev = SPI_DEV; + device_t dev = PCH_DEV_SPI; uint8_t val;
/* Disable Bus Master and MMIO space. */ @@ -135,7 +135,7 @@
static void enable_pmcbar(void) { - device_t pmc = PMC_DEV; + device_t pmc = PCH_DEV_PMC;
/* Set PMC base addresses and enable decoding. */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 2973abf..71706d0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -54,59 +54,59 @@
switch (dev->path.pci.devfn) { /* DSDT: acpi/northbridge.asl */ - case NB_DEVFN: + case SA_DEVFN_ROOT: return "MCHC"; /* DSDT: acpi/lpc.asl */ - case LPC_DEVFN: + case PCH_DEVFN_LPC: return "LPCB"; /* DSDT: acpi/xhci.asl */ - case XHCI_DEVFN: + case PCH_DEVFN_XHCI: return "XHCI"; /* DSDT: acpi/pch_hda.asl */ - case HDA_DEVFN: + case PCH_DEVFN_HDA: return "HDAS"; /* DSDT: acpi/lpss.asl */ - case LPSS_DEVFN_UART0: + case PCH_DEVFN_UART0: return "URT1"; - case LPSS_DEVFN_UART1: + case PCH_DEVFN_UART1: return "URT2"; - case LPSS_DEVFN_UART2: + case PCH_DEVFN_UART2: return "URT3"; - case LPSS_DEVFN_UART3: + case PCH_DEVFN_UART3: return "URT4"; - case LPSS_DEVFN_SPI0: + case PCH_DEVFN_SPI0: return "SPI1"; - case LPSS_DEVFN_SPI1: + case PCH_DEVFN_SPI1: return "SPI2"; - case LPSS_DEVFN_SPI2: + case PCH_DEVFN_SPI2: return "SPI3"; - case LPSS_DEVFN_PWM: + case PCH_DEVFN_PWM: return "PWM"; - case LPSS_DEVFN_I2C0: + case PCH_DEVFN_I2C0: return "I2C0"; - case LPSS_DEVFN_I2C1: + case PCH_DEVFN_I2C1: return "I2C1"; - case LPSS_DEVFN_I2C2: + case PCH_DEVFN_I2C2: return "I2C2"; - case LPSS_DEVFN_I2C3: + case PCH_DEVFN_I2C3: return "I2C3"; - case LPSS_DEVFN_I2C4: + case PCH_DEVFN_I2C4: return "I2C4"; - case LPSS_DEVFN_I2C5: + case PCH_DEVFN_I2C5: return "I2C5"; - case LPSS_DEVFN_I2C6: + case PCH_DEVFN_I2C6: return "I2C6"; - case LPSS_DEVFN_I2C7: + case PCH_DEVFN_I2C7: return "I2C7"; /* Storage */ - case SDCARD_DEVFN: + case PCH_DEVFN_SDCARD: return "SDCD"; - case EMMC_DEVFN: + case PCH_DEVFN_EMMC: return "EMMC"; - case SDIO_DEVFN: + case PCH_DEVFN_SDIO: return "SDIO"; /* PCIe */ - case PCIEB0_DEVFN: + case PCH_DEVFN_PCIE1: return "RP01"; }
@@ -205,15 +205,15 @@
static void pcie_override_devicetree_after_silicon_init(void) { - pcie_update_device_tree(PCIEA0_DEVFN, 4); - pcie_update_device_tree(PCIEB0_DEVFN, 2); + pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); + pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); }
/* Configure package power limits */ static void set_power_limits(void) { static struct soc_intel_apollolake_config *cfg; - struct device *dev = NB_DEV_ROOT; + struct device *dev = SA_DEV_ROOT; msr_t rapl_msr_reg, limit; uint32_t power_unit; uint32_t tdp, min_power, max_power; @@ -329,97 +329,97 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { switch (dev->path.pci.devfn) { - case ISH_DEVFN: + case PCH_DEVFN_ISH: silconfig->IshEnable = 0; break; - case SATA_DEVFN: + case PCH_DEVFN_SATA: silconfig->EnableSata = 0; break; - case PCIEB0_DEVFN: + case PCH_DEVFN_PCIE5: silconfig->PcieRootPortEn[0] = 0; silconfig->PcieRpHotPlug[0] = 0; break; - case PCIEB1_DEVFN: + case PCH_DEVFN_PCIE6: silconfig->PcieRootPortEn[1] = 0; silconfig->PcieRpHotPlug[1] = 0; break; - case PCIEA0_DEVFN: + case PCH_DEVFN_PCIE1: silconfig->PcieRootPortEn[2] = 0; silconfig->PcieRpHotPlug[2] = 0; break; - case PCIEA1_DEVFN: + case PCH_DEVFN_PCIE2: silconfig->PcieRootPortEn[3] = 0; silconfig->PcieRpHotPlug[3] = 0; break; - case PCIEA2_DEVFN: + case PCH_DEVFN_PCIE3: silconfig->PcieRootPortEn[4] = 0; silconfig->PcieRpHotPlug[4] = 0; break; - case PCIEA3_DEVFN: + case PCH_DEVFN_PCIE4: silconfig->PcieRootPortEn[5] = 0; silconfig->PcieRpHotPlug[5] = 0; break; - case XHCI_DEVFN: + case PCH_DEVFN_XHCI: silconfig->Usb30Mode = 0; break; - case XDCI_DEVFN: + case PCH_DEVFN_XDCI: silconfig->UsbOtg = 0; break; - case LPSS_DEVFN_I2C0: + case PCH_DEVFN_I2C0: silconfig->I2c0Enable = 0; break; - case LPSS_DEVFN_I2C1: + case PCH_DEVFN_I2C1: silconfig->I2c1Enable = 0; break; - case LPSS_DEVFN_I2C2: + case PCH_DEVFN_I2C2: silconfig->I2c2Enable = 0; break; - case LPSS_DEVFN_I2C3: + case PCH_DEVFN_I2C3: silconfig->I2c3Enable = 0; break; - case LPSS_DEVFN_I2C4: + case PCH_DEVFN_I2C4: silconfig->I2c4Enable = 0; break; - case LPSS_DEVFN_I2C5: + case PCH_DEVFN_I2C5: silconfig->I2c5Enable = 0; break; - case LPSS_DEVFN_I2C6: + case PCH_DEVFN_I2C6: silconfig->I2c6Enable = 0; break; - case LPSS_DEVFN_I2C7: + case PCH_DEVFN_I2C7: silconfig->I2c7Enable = 0; break; - case LPSS_DEVFN_UART0: + case PCH_DEVFN_UART0: silconfig->Hsuart0Enable = 0; break; - case LPSS_DEVFN_UART1: + case PCH_DEVFN_UART1: silconfig->Hsuart1Enable = 0; break; - case LPSS_DEVFN_UART2: + case PCH_DEVFN_UART2: silconfig->Hsuart2Enable = 0; break; - case LPSS_DEVFN_UART3: + case PCH_DEVFN_UART3: silconfig->Hsuart3Enable = 0; break; - case LPSS_DEVFN_SPI0: + case PCH_DEVFN_SPI0: silconfig->Spi0Enable = 0; break; - case LPSS_DEVFN_SPI1: + case PCH_DEVFN_SPI1: silconfig->Spi1Enable = 0; break; - case LPSS_DEVFN_SPI2: + case PCH_DEVFN_SPI2: silconfig->Spi2Enable = 0; break; - case SDCARD_DEVFN: + case PCH_DEVFN_SDCARD: silconfig->SdcardEnabled = 0; break; - case EMMC_DEVFN: + case PCH_DEVFN_EMMC: silconfig->eMMCEnabled = 0; break; - case SDIO_DEVFN: + case PCH_DEVFN_SDIO: silconfig->SdioEnabled = 0; break; - case SMBUS_DEVFN: + case PCH_DEVFN_SMBUS: silconfig->SmbusEnable = 0; break; default: @@ -432,7 +432,7 @@
static void parse_devicetree(FSP_S_CONFIG *silconfig) { - struct device *dev = NB_DEV_ROOT; + struct device *dev = SA_DEV_ROOT;
if (!dev) { printk(BIOS_ERR, "Could not find root device\n"); @@ -454,7 +454,7 @@ /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt;
- struct device *dev = NB_DEV_ROOT; + struct device *dev = SA_DEV_ROOT;
if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index a7c888a..a571a65 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -175,7 +175,7 @@
static uint32_t dump_status(int index, int reg_addr) { - uint32_t reg = pci_read_config32(HECI1_DEV, reg_addr); + uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr);
printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg);
diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c index d0bc4fa..95f540c 100644 --- a/src/soc/intel/apollolake/flash_ctrlr.c +++ b/src/soc/intel/apollolake/flash_ctrlr.c @@ -60,7 +60,7 @@ uint32_t bar;
/* FIXME: use device definition */ - ctx->pci_dev = SPI_DEV; + ctx->pci_dev = PCH_DEV_SPI;
bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 18348e36..9963d2c 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -28,7 +28,7 @@
uintptr_t fsp_soc_get_igd_bar(void) { - return find_resource(IGD_DEV, PCI_BASE_ADDRESS_2)->base; + return find_resource(SA_DEV_IGD, PCI_BASE_ADDRESS_2)->base; }
static void igd_set_resources(struct device *dev) diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index 55da98c..000fe23 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -22,7 +22,7 @@
uint32_t heci_fw_sts(void) { - return pci_read_config32(HECI1_DEV, REG_SEC_FW_STS0); + return pci_read_config32(PCH_DEV_CSE, REG_SEC_FW_STS0); }
bool heci_cse_normal(void) diff --git a/src/soc/intel/apollolake/include/soc/i2c.h b/src/soc/intel/apollolake/include/soc/i2c.h index de1a04a..f7778e5 100644 --- a/src/soc/intel/apollolake/include/soc/i2c.h +++ b/src/soc/intel/apollolake/include/soc/i2c.h @@ -29,9 +29,9 @@ static inline int i2c_bus_to_devfn(unsigned int bus) { if (bus >= 0 && bus <= 3) - return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D0, bus); + return PCI_DEVFN(PCH_DEV_SLOT_SIO1, bus); else if (bus >= 4 && bus <= 7) - return PCI_DEVFN(LPSS_DEV_SLOT_I2C_D1, (bus - 4)); + return PCI_DEVFN(PCH_DEV_SLOT_SIO2, (bus - 4)); else return -1; } @@ -39,9 +39,9 @@ /* Convert PCI device and function to I2C bus number */ static inline int i2c_devfn_to_bus(unsigned int devfn) { - if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D0) + if (PCI_SLOT(devfn) == PCH_DEV_SLOT_SIO1) return PCI_FUNC(devfn); - else if (PCI_SLOT(devfn) == LPSS_DEV_SLOT_I2C_D1) + else if (PCI_SLOT(devfn) == PCH_DEV_SLOT_SIO2) return PCI_FUNC(devfn) + 4; else return -1; diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 3e4dcb2..6aa2520 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -15,112 +15,147 @@ #ifndef _SOC_APOLLOLAKE_PCI_DEVS_H_ #define _SOC_APOLLOLAKE_PCI_DEVS_H_
+#include <device/pci_def.h> #include <rules.h>
-#define _LPSS_PCI_DEVFN(slot, func) PCI_DEVFN(LPSS_DEV_SLOT_##slot, func) -#define _PCI_DEVFN(slot, func) PCI_DEVFN(slot, func) +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> -#define _LPSS_PCI_DEV(slot, func) dev_find_slot(0, _LPSS_PCI_DEVFN(slot, \ - func)) -#define _PCI_DEV(slot, func) dev_find_slot(0, PCI_DEVFN(slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else #include <arch/io.h> -#define _LPSS_PCI_DEV(slot, func) PCI_DEV(0, LPSS_DEV_SLOT_##slot, func) -#define _PCI_DEV(slot, func) PCI_DEV(0, slot, func) +#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif
-#define NB_DEVFN _PCI_DEVFN(0, 0) -#define NB_DEV_ROOT _PCI_DEV(0x0, 0) +/* System Agent Devices */
-#define PUNIT_DEV _PCI_DEV(0, 1) -#define PUNIT_DEVFN _PCI_DEVFN(0x0, 1) +#define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) +#define SA_DEV_ROOT _SA_DEV(ROOT)
-#define IGD_DEV _PCI_DEV(0x2, 0) -#define IGD_DEVFN _PCI_DEVFN(0x2, 0) +#define SA_DEV_SLOT_PUNIT 0x01 +#define SA_DEVFN_PUNIT _SA_DEVFN(PUNIT) +#define SA_DEV_PUNIT _SA_DEV(PUNIT)
-#define P2SB_DEV _PCI_DEV(0xd, 0) -#define P2SB_DEVFN _PCI_DEVFN(0xd, 0) +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD)
-#define PMC_DEV _PCI_DEV(0xd, 1) -#define PMC_DEVFN _PCI_DEVFN(0xd, 1) +/* PCH Devices */
-#define SPI_DEV _PCI_DEV(0xd, 2) -#define SPI_DEVFN _PCI_DEVFN(0xd, 2) +#define PCH_DEV_SLOT_P2SB 0x0d +#define PCH_DEVFN_P2SB _PCH_DEVFN(P2SB, 0) +#define PCH_DEVFN_PMC _PCH_DEVFN(P2SB, 1) +#define PCH_DEVFN_SPI _PCH_DEVFN(P2SB, 2) +#define PCH_DEV_P2SB _PCH_DEV(P2SB, 0) +#define PCH_DEV_PMC _PCH_DEV(P2SB, 1) +#define PCH_DEV_SPI _PCH_DEV(P2SB, 2)
-#define HDA_DEV _PCI_DEV(0xe, 0) -#define HDA_DEVFN _PCI_DEVFN(0xe, 0) +#define PCH_DEV_SLOT_HDA 0x0e +#define PCH_DEVFN_HDA _PCH_DEVFN(HDA, 0) +#define PCH_DEV_HDA _PCH_DEV(HDA, 0)
-#define HECI1_DEV _PCI_DEV(0xf, 0) -#define HECI1_DEVFN _PCI_DEVFN(0xf, 0) +#define PCH_DEV_SLOT_CSE 0x0f +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
-#define ISH_DEV _PCI_DEV(0x11, 0) -#define ISH_DEVFN _PCI_DEVFN(0x11, 0) +#define PCH_DEV_SLOT_ISH 0x11 +#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0) +#define PCH_DEV_ISH _PCH_DEV(ISH, 0)
-#define SATA_DEV _PCI_DEV(0x12, 0) -#define SATA_DEVFN _PCI_DEVFN(0x12, 0) +#define PCH_DEV_SLOT_SATA 0x12 +#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) +#define PCH_DEV_SATA _PCH_DEV(SATA, 0)
-#define PCIEA0_DEVFN _PCI_DEVFN(0x13, 0) -#define PCIEA1_DEVFN _PCI_DEVFN(0x13, 1) -#define PCIEA2_DEVFN _PCI_DEVFN(0x13, 2) -#define PCIEA3_DEVFN _PCI_DEVFN(0x13, 3) -#define PCIEB0_DEVFN _PCI_DEVFN(0x14, 0) -#define PCIEB1_DEVFN _PCI_DEVFN(0x14, 1) +#define PCH_DEV_SLOT_PCIE 0x13 +#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0) +#define PCH_DEVFN_PCIE2 _PCH_DEVFN(PCIE, 1) +#define PCH_DEVFN_PCIE3 _PCH_DEVFN(PCIE, 2) +#define PCH_DEVFN_PCIE4 _PCH_DEVFN(PCIE, 3) +#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0) +#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1) +#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2) +#define PCH_DEV_PCIE4 _PCH_DEV(PCIE, 3)
-#define XHCI_DEV _PCI_DEV(0x15, 0) -#define XHCI_DEVFN _PCI_DEVFN(0x15, 0) +#define PCH_DEV_SLOT_PCIE_1 0x14 +#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE_1, 0) +#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE_1, 1) +#define PCH_DEV_PCIE5 _PCH_DEV(PCIE_1, 0) +#define PCH_DEV_PCIE6 _PCH_DEV(PCIE_1, 1)
-#define XDCI_DEV _PCI_DEV(0x15, 1) -#define XDCI_DEVFN _PCI_DEVFN(0x15, 1) +#define PCH_DEV_SLOT_XHCI 0x15 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEVFN_XDCI _PCH_DEVFN(XHCI, 1) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) +#define PCH_DEV_XDCI _PCH_DEV(XHCI, 1)
/* LPSS I2C, 2 devices cover 8 controllers */ -#define LPSS_DEV_SLOT_I2C_D0 0x16 -#define LPSS_DEVFN_I2C0 _LPSS_PCI_DEVFN(I2C_D0, 0) -#define LPSS_DEVFN_I2C1 _LPSS_PCI_DEVFN(I2C_D0, 1) -#define LPSS_DEVFN_I2C2 _LPSS_PCI_DEVFN(I2C_D0, 2) -#define LPSS_DEVFN_I2C3 _LPSS_PCI_DEVFN(I2C_D0, 3) -#define LPSS_DEV_SLOT_I2C_D1 0x17 -#define LPSS_DEVFN_I2C4 _LPSS_PCI_DEVFN(I2C_D1, 0) -#define LPSS_DEVFN_I2C5 _LPSS_PCI_DEVFN(I2C_D1, 1) -#define LPSS_DEVFN_I2C6 _LPSS_PCI_DEVFN(I2C_D1, 2) -#define LPSS_DEVFN_I2C7 _LPSS_PCI_DEVFN(I2C_D1, 3) +#define PCH_DEV_SLOT_SIO1 0x16 +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1) +#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2) +#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3) +#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0) +#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1) +#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) +#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3) + +#define PCH_DEV_SLOT_SIO2 0x17 +#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0) +#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1) +#define PCH_DEVFN_I2C6 _PCH_DEVFN(SIO2, 2) +#define PCH_DEVFN_I2C7 _PCH_DEVFN(SIO2, 3) +#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0) +#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1) +#define PCH_DEV_I2C6 _PCH_DEV(SIO2, 2) +#define PCH_DEV_I2C7 _PCH_DEV(SIO2, 3)
/* LPSS UART */ -#define LPSS_DEV_SLOT_UART 0x18 -#define LPSS_DEVFN_UART0 _LPSS_PCI_DEVFN(UART, 0) -#define LPSS_DEVFN_UART1 _LPSS_PCI_DEVFN(UART, 1) -#define LPSS_DEVFN_UART2 _LPSS_PCI_DEVFN(UART, 2) -#define LPSS_DEVFN_UART3 _LPSS_PCI_DEVFN(UART, 3) -#define LPSS_DEV_UART0 _LPSS_PCI_DEV(UART, 0) -#define LPSS_DEV_UART1 _LPSS_PCI_DEV(UART, 1) -#define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) -#define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define PCH_DEV_SLOT_UART 0x18 +#define PCH_DEVFN_UART0 _PCH_DEVFN(UART, 0) +#define PCH_DEVFN_UART1 _PCH_DEVFN(UART, 1) +#define PCH_DEVFN_UART2 _PCH_DEVFN(UART, 2) +#define PCH_DEVFN_UART3 _PCH_DEVFN(UART, 3) +#define PCH_DEV_UART0 _PCH_DEV(UART, 0) +#define PCH_DEV_UART1 _PCH_DEV(UART, 1) +#define PCH_DEV_UART2 _PCH_DEV(UART, 2) +#define PCH_DEV_UART3 _PCH_DEV(UART, 3)
/* LPSS SPI */ -#define LPSS_DEV_SLOT_SPI 0x19 -#define LPSS_DEVFN_SPI0 _LPSS_PCI_DEVFN(SPI, 0) -#define LPSS_DEVFN_SPI1 _LPSS_PCI_DEVFN(SPI, 1) -#define LPSS_DEVFN_SPI2 _LPSS_PCI_DEVFN(SPI, 2) +#define PCH_DEV_SLOT_SPI 0x19 +#define PCH_DEVFN_SPI0 _PCH_DEVFN(SPI, 0) +#define PCH_DEVFN_SPI1 _PCH_DEVFN(SPI, 1) +#define PCH_DEVFN_SPI2 _PCH_DEVFN(SPI, 2) +#define PCH_DEV_SPI0 _PCH_DEV(SPI, 0) +#define PCH_DEV_SPI1 _PCH_DEV(SPI, 1) +#define PCH_DEV_SPI2 _PCH_DEV(SPI, 2)
/* LPSS PWM */ -#define LPSS_DEV_SLOT_PWM 0x1a -#define LPSS_DEVFN_PWM _LPSS_PCI_DEVFN(PWM, 0) +#define PCH_DEV_SLOT_PWM 0x1a +#define PCH_DEVFN_PWM _PCH_DEVFN(PWM, 0) +#define PCH_DEV_PWM _PCH_DEV(PWM, 0)
-#define SDCARD_DEV _PCI_DEV(0x1b, 0) -#define SDCARD_DEVFN _PCI_DEVFN(0x1b, 0) +#define PCH_DEV_SLOT_SDCARD 0x1b +#define PCH_DEVFN_SDCARD _PCH_DEVFN(SDCARD, 0) +#define PCH_DEV_SDCARD _PCH_DEV(SDCARD, 0)
-#define EMMC_DEV _PCI_DEV(0x1c, 0) -#define EMMC_DEVFN _PCI_DEVFN(0x1c, 0) +#define PCH_DEV_SLOT_EMMC 0x1c +#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) +#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0)
-#define SDIO_DEV _PCI_DEV(0x1e, 0) -#define SDIO_DEVFN _PCI_DEVFN(0x1e, 0) +#define PCH_DEV_SLOT_SDIO 0x1e +#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0) +#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0)
-#define LPC_DEV _PCI_DEV(0x1f, 0) -#define LPC_DEVFN _PCI_DEVFN(0x1f, 0) - -#define SMBUS_DEV _PCI_DEV(0x1f, 1) -#define SMBUS_DEVFN _PCI_DEVFN(0x1f, 1) +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 1) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 1)
#endif diff --git a/src/soc/intel/apollolake/lpc_lib.c b/src/soc/intel/apollolake/lpc_lib.c index f435047..08c16a7 100644 --- a/src/soc/intel/apollolake/lpc_lib.c +++ b/src/soc/intel/apollolake/lpc_lib.c @@ -66,9 +66,9 @@ { uint16_t reg_io_enables;
- reg_io_enables = pci_read_config16(LPC_DEV, REG_IO_ENABLES); + reg_io_enables = pci_read_config16(PCH_DEV_LPC, REG_IO_ENABLES); io_enables |= reg_io_enables; - pci_write_config16(LPC_DEV, REG_IO_ENABLES, io_enables); + pci_write_config16(PCH_DEV_LPC, REG_IO_ENABLES, io_enables); }
/* @@ -81,7 +81,7 @@ uint32_t lgir;
for (i = 0; i < NUM_GENERIC_IO_RANGES; i++) { - lgir = pci_read_config32(LPC_DEV, REG_GENERIC_IO_RANGE(i)); + lgir = pci_read_config32(PCH_DEV_LPC, REG_GENERIC_IO_RANGE(i));
if (!(lgir & LGIR_EN)) return i; @@ -95,7 +95,7 @@ size_t i;
for (i = 0; i < NUM_GENERIC_IO_RANGES; i++) - pci_write_config32(LPC_DEV, REG_GENERIC_IO_RANGE(i), 0); + pci_write_config32(PCH_DEV_LPC, REG_GENERIC_IO_RANGE(i), 0); }
void lpc_open_pmio_window(uint16_t base, uint16_t size) @@ -132,7 +132,7 @@ lgir = (bridge_base & LGIR_ADDR_MASK) | LGIR_EN; lgir |= ((window_size - 1) << 16) & LGIR_AMASK_MASK;
- pci_write_config32(LPC_DEV, lgir_reg_offset, lgir); + pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", @@ -147,7 +147,7 @@ { uint32_t lgmr;
- lgmr = pci_read_config32(LPC_DEV, REG_GENERIC_MEM_RANGE); + lgmr = pci_read_config32(PCH_DEV_LPC, REG_GENERIC_MEM_RANGE);
if (lgmr & LGMR_EN) { printk(BIOS_ERR, @@ -165,7 +165,7 @@
lgmr = (base & LGMR_ADDR_MASK) | LGMR_EN;
- pci_write_config32(LPC_DEV, REG_GENERIC_MEM_RANGE, lgmr); + pci_write_config32(PCH_DEV_LPC, REG_GENERIC_MEM_RANGE, lgmr); }
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index cccbffd..a10477c 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -33,13 +33,13 @@
static uintptr_t smm_region_start(void) { - return ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, TSEG), 1*MiB); + return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, TSEG), 1*MiB); }
static size_t smm_region_size(void) { uintptr_t smm_end = - ALIGN_DOWN(pci_read_config32(NB_DEV_ROOT, BGSM), 1*MiB); + ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, BGSM), 1*MiB); return smm_end - smm_region_start(); }
diff --git a/src/soc/intel/apollolake/p2sb.c b/src/soc/intel/apollolake/p2sb.c index 7834e38..8056d14 100644 --- a/src/soc/intel/apollolake/p2sb.c +++ b/src/soc/intel/apollolake/p2sb.c @@ -34,7 +34,7 @@ const uint8_t mask = HIDE_BIT; uint8_t val;
- dev = P2SB_DEV; + dev = PCH_DEV_P2SB;
val = pci_read_config8(dev, reg); val &= ~mask; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index f2bb0ee..7d3cb07 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -505,7 +505,7 @@ ROMSTAGE_CONST struct soc_intel_apollolake_config *config;
/* Look up the device in devicetree */ - ROMSTAGE_CONST struct device *dev = dev_find_slot(0, NB_DEVFN); + ROMSTAGE_CONST struct device *dev = SA_DEV_ROOT; if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 93b571e..38cf81c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -80,10 +80,10 @@ static void soc_early_romstage_init(void) { /* Set MCH base address and enable bit */ - pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1);
/* Enable decoding for HPET. Needed for FSP global pointer storage */ - pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | + pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); }
@@ -140,7 +140,7 @@ return false; } /* Set Punit interrupt pin IPIN offset 3D */ - pci_write_config8(PUNIT_DEVFN, PCI_INTERRUPT_PIN, 0x2); + pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2);
/* Set PUINT IRQ to 24 and INTPIN LOCK */ write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), diff --git a/src/soc/intel/apollolake/smihandler.c b/src/soc/intel/apollolake/smihandler.c index b84e5cb..0272a5c 100644 --- a/src/soc/intel/apollolake/smihandler.c +++ b/src/soc/intel/apollolake/smihandler.c @@ -34,7 +34,7 @@
int smm_disable_busmaster(device_t dev) { - if (dev == PMC_DEV) + if (dev == PCH_DEV_PMC) return 0; return 1; } diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 7b50a21..70d034f 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -32,7 +32,7 @@ pci_dev_read_resources(dev);
if ((IS_ENABLED(CONFIG_SOC_UART_DEBUG) && - dev->path.pci.devfn == _LPSS_PCI_DEVFN(UART, + dev->path.pci.devfn == _PCH_DEVFN(UART, CONFIG_UART_FOR_CONSOLE))) { /* will override existing resource. */ fixed_mem_resource(dev, PCI_BASE_ADDRESS_0, diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index 173e8a1..51aeedf 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -39,7 +39,7 @@ void lpss_console_uart_init(void) { uint32_t clk_sel; - device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); + device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3);
if (invalid_uart_for_console()) return; diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c index 2812957..22abec9 100644 --- a/src/soc/intel/apollolake/xdci.c +++ b/src/soc/intel/apollolake/xdci.c @@ -48,7 +48,7 @@ const struct resource *res; uint32_t reg; struct stopwatch sw; - struct device *xhci_dev = XHCI_DEV; + struct device *xhci_dev = PCH_DEV_XHCI;
/* * Only default to host mode if the xdci device is present and diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 3808bd6..64a20d8 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -80,7 +80,7 @@ void heci_init(uintptr_t tempbar) { struct cse_device *cse = car_get_var_ptr(&g_cse); - device_t dev = HECI1_DEV; + device_t dev = PCH_DEV_CSE; u8 pcireg;
/* Assume it is already initialized, nothing else to do */ @@ -453,7 +453,7 @@
static void cse_set_resources(struct device *dev) { - if (dev->path.pci.devfn == HECI1_DEVFN) + if (dev->path.pci.devfn == PCH_DEVFN_CSE) update_sec_bar(dev);
pci_dev_set_resources(dev); diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index d711434..b3b999f 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -653,11 +653,11 @@ case PCH_DEVFN_I2C1: return "I2C1"; case PCH_DEVFN_I2C2: return "I2C2"; case PCH_DEVFN_I2C3: return "I2C3"; - case PCH_DEVFN_ME: return "MEI1"; - case PCH_DEVFN_ME_2: return "MEI2"; - case PCH_DEVFN_ME_IDER: return "MEID"; - case PCH_DEVFN_ME_KT: return "MEKT"; - case PCH_DEVFN_ME_3: return "MEI3"; + case PCH_DEVFN_CSE: return "CSE1"; + case PCH_DEVFN_CSE_2: return "CSE2"; + case PCH_DEVFN_CSE_IDER: return "CSED"; + case PCH_DEVFN_CSE_KT: return "CSKT"; + case PCH_DEVFN_CSE_3: return "CSE3"; case PCH_DEVFN_SATA: return "SATA"; case PCH_DEVFN_UART2: return "UAR2"; case PCH_DEVFN_I2C4: return "I2C4"; diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 62054f1..60b22dc 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -242,7 +242,7 @@
static void enable_heci(void) { - device_t dev = PCH_DEV_ME; + device_t dev = PCH_DEV_CSE; u8 pcireg;
/* Assign Resources to HECI1 */ diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index 10d4806..469d7e9 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */
-#ifndef _SOC_PCI_DEVS_H_ -#define _SOC_PCI_DEVS_H_ +#ifndef _SOC_SKYLAKE_PCI_DEVS_H_ +#define _SOC_SKYLAKE_PCI_DEVS_H_
#include <device/pci_def.h> #include <rules.h> @@ -23,7 +23,7 @@ #define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)
-#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if !defined(__SIMPLE_DEVICE__) #include <device/device.h> #include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) @@ -72,17 +72,17 @@ #define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2) #define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3)
-#define PCH_DEV_SLOT_ME 0x16 -#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0) -#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1) -#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2) -#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3) -#define PCH_DEVFN_ME_3 _PCH_DEVFN(ME, 4) -#define PCH_DEV_ME _PCH_DEV(ME, 0) -#define PCH_DEV_ME_2 _PCH_DEV(ME, 1) -#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2) -#define PCH_DEV_ME_KT _PCH_DEV(ME, 3) -#define PCH_DEV_ME_3 _PCH_DEV(ME, 4) +#define PCH_DEV_SLOT_CSE 0x16 +#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0) +#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1) +#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2) +#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3) +#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4) +#define PCH_DEV_CSE _PCH_DEV(CSE, 0) +#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1) +#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2) +#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3) +#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
#define PCH_DEV_SLOT_SATA 0x17 #define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0) diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 6d3aa7b..649f137 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -157,20 +157,20 @@ DEVICE_INT_CONFIG(PCH_DEV_SLOT_SATA, PCI_FUNC(PCH_DEVFN_SATA), int_A, SATA_IRQ), /* CSME: HECI #1 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, - PCI_FUNC(PCH_DEVFN_ME), int_A, HECI_1_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, + PCI_FUNC(PCH_DEVFN_CSE), int_A, HECI_1_IRQ), /* CSME: HECI #2 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, - PCI_FUNC(PCH_DEVFN_ME_2), int_B, HECI_2_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, + PCI_FUNC(PCH_DEVFN_CSE_2), int_B, HECI_2_IRQ), /* CSME: IDE-Redirection (IDE-R) */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, - PCI_FUNC(PCH_DEVFN_ME_IDER), int_C, IDER_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, + PCI_FUNC(PCH_DEVFN_CSE_IDER), int_C, IDER_IRQ), /* CSME: Keyboard and Text (KT) Redirection */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, - PCI_FUNC(PCH_DEVFN_ME_KT), int_D, KT_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, + PCI_FUNC(PCH_DEVFN_CSE_KT), int_D, KT_IRQ), /* CSME: HECI #3 */ - DEVICE_INT_CONFIG(PCH_DEV_SLOT_ME, - PCI_FUNC(PCH_DEVFN_ME_3), int_A, HECI_3_IRQ), + DEVICE_INT_CONFIG(PCH_DEV_SLOT_CSE, + PCI_FUNC(PCH_DEVFN_CSE_3), int_A, HECI_3_IRQ), /* * SerialIo I2C Controller #0, INTA is default, * programmed in PCR[SERIALIO] + PCICFGCTRL[1] diff --git a/src/soc/intel/skylake/me.c b/src/soc/intel/skylake/me.c index 5774372..5bc5c95 100644 --- a/src/soc/intel/skylake/me.c +++ b/src/soc/intel/skylake/me.c @@ -30,12 +30,12 @@
static inline u32 me_read_config32(int offset) { - return pci_read_config32(PCH_DEV_ME, offset); + return pci_read_config32(PCH_DEV_CSE, offset); }
static inline void me_write_config32(int offset, u32 value) { - pci_write_config32(PCH_DEV_ME, offset, value); + pci_write_config32(PCH_DEV_CSE, offset, value); }
static inline u32 me_read_mmio32(int offset)
-
Martin Roth (Code Review)