Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Werner Zeh, Patrick Rudolph.
Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61520 )

Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................

Patch Set 6:

(1 comment)

File src/soc/intel/common/block/cse/cse.c:

https://review.coreboot.org/c/coreboot/+/61520/comment/8a0b44b1_88969b88 
PS6, Line 1018: (cse_is_hfs1_com_normal() || cse_is_hfs1_com_soft_temp_disable())
> didn't get u ?

Only BIOS should have capability to trigger global reset and sending GLOBAL RESET MEI message.
Recommendations as follow:

1. BIOS should send GLOBAL RESET MEI command if CSE is not in error state and not sent EOP command before. This is to avoid the synchronization issues between host and CSE.

2. If CSE is in error state, *BIOS* should trigger global reset by setting PCH register(I/O 0xCF9 write of 06h or 0Eh command with PMC PWRM offset 1048h register bit [20] CF9GR).

3. If FWSTS1[4] (non-production environment) is set, allow OS to trigger global reset by setting the PCH register(as said in Point#2) . In this scenario, BIOS shouldn't lock global reset config.