Mimoja has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37986 )
Change subject: util/inteltool: Add chip detection for IceLake chips ......................................................................
util/inteltool: Add chip detection for IceLake chips
So far inteltool does not detect the Icelake U CPU, North- and Southbridge so far. To prepare for GPIO dumping this commit adds the required identifiers.
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410 Signed-off-by: Johanna Schander coreboot@mimoja.de --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/37986/1
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 830cdcd..de66811 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -139,6 +139,8 @@ "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U, + "10th generation (Icelake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -216,6 +218,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_U, + "Icelake U LPC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, @@ -433,6 +437,8 @@ "Intel(R) Iris Plus Graphics 650" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655, "Intel(R) Iris Plus Graphics 655" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7, + "Intel(R) Iris Plus Graphics G7" }, };
#ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..1c1841c 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -106,6 +106,7 @@ #define PCI_DEVICE_ID_INTEL_3450 0x3b16 #define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482 #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 #define PCI_DEVICE_ID_INTEL_P67 0x1c46 #define PCI_DEVICE_ID_INTEL_UM67 0x1c47 @@ -291,6 +292,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */
/* Intel GPUs */ @@ -359,6 +361,7 @@ #define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 +#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t;
Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37986 )
Change subject: util/inteltool: Add chip detection for IceLake chips ......................................................................
Patch Set 1: Code-Review+1
Hello Christoph Pomaska, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37986
to look at the new patch set (#2).
Change subject: util/inteltool: Add chip detection for IceLake chips ......................................................................
util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410 Signed-off-by: Johanna Schander coreboot@mimoja.de --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/37986/2
Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37986 )
Change subject: util/inteltool: Add chip detection for IceLake chips ......................................................................
Patch Set 2: Code-Review+2
Philipp Deppenwiese has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37986 )
Change subject: util/inteltool: Add chip detection for IceLake chips ......................................................................
util/inteltool: Add chip detection for IceLake chips
Change-Id: Ia4752391e1232ac67d8927778a3a94eec5c68410 Signed-off-by: Johanna Schander coreboot@mimoja.de Reviewed-on: https://review.coreboot.org/c/coreboot/+/37986 Reviewed-by: Philipp Deppenwiese zaolin.daisuki@gmail.com Reviewed-by: Christoph Pomaska github@aufmachen.jetzt Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M util/inteltool/inteltool.c M util/inteltool/inteltool.h 2 files changed, 9 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Christoph Pomaska: Looks good to me, but someone else must approve
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 830cdcd..de66811 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -139,6 +139,8 @@ "7th generation (Kaby Lake family) Core Processor (Mobile)" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3, "7th generation (Kaby Lake family) Core Processor Xeon E3-1200" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U, + "10th generation (Icelake family) Core Processor (Mobile)" }, /* Southbridges (LPC controllers) */ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, @@ -216,6 +218,8 @@ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM75, "HM75" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM70, "HM70" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM70, "NM70" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_U, + "Icelake U LPC" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL, "Lynx Point Low Power Full Featured Engineering Sample" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM, @@ -433,6 +437,8 @@ "Intel(R) Iris Plus Graphics 650" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_655, "Intel(R) Iris Plus Graphics 655" }, + { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7, + "Intel(R) Iris Plus Graphics G7" }, };
#ifndef __DARWIN__ diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index fc6dc4b..1c1841c 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -106,6 +106,7 @@ #define PCI_DEVICE_ID_INTEL_3450 0x3b16 #define PCI_DEVICE_ID_INTEL_B55_B 0x3b1e #define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119 +#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_U 0x3482 #define PCI_DEVICE_ID_INTEL_Z68 0x1c44 #define PCI_DEVICE_ID_INTEL_P67 0x1c46 #define PCI_DEVICE_ID_INTEL_UM67 0x1c47 @@ -291,6 +292,7 @@ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_E3 0x5918 /* Kabylake Xeon E3 */ +#define PCI_DEVICE_ID_INTEL_CORE_10TH_GEN_U 0x8a12 /* Icelake U */
/* Intel GPUs */ @@ -359,6 +361,7 @@ #define PCI_DEVICE_ID_INTEL_IRIS_PRO_580 0x193B #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_650 0x5927 #define PCI_DEVICE_ID_INTEL_IRIS_PLUS_655 0x3EA5 +#define PCI_DEVICE_ID_INTEL_IRIS_PLUS_G7 0x8A52
#if !defined(__DARWIN__) && !defined(__FreeBSD__) typedef struct { uint32_t hi, lo; } msr_t;
-
Christoph Pomaska (Code Review) -
Mimoja (Code Review)
-
Philipp Deppenwiese (Code Review)