Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 )

Change subject: {drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
......................................................................

Patch Set 47:

(1 comment)

https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_r... 
File src/drivers/intel/fsp1_1/cache_as_ram.S:

https://review.coreboot.org/#/c/29662/47/src/drivers/intel/fsp1_1/cache_as_r... 
PS47, Line 57: 	jmp	find_fsp
> But it should have been. The called code is compiled by a different
> compiler now, afaict (romcc vs gcc).

That is not true. This was previously compiled into romstage by GCC.
The only functional difference the romcc bootblock updated microcode and set up MTRR's to speed up the cbfs walk and then jumped to this code, but this was already ruled out to be the problem. Just doing finding the cbfsfile and comparing that CONFIG_FSP_LOC should do the trick?