[M] Change in coreboot[main]: soc/intel/xeon_sp: Create CXL domains

[Arthur Heymans (Code Review)]

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81099?usp=email )

Change subject: soc/intel/xeon_sp: Create CXL domains
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Patch Set 4:

(1 comment)

File src/soc/intel/xeon_sp/chip_common.c:

https://review.coreboot.org/c/coreboot/+/81099/comment/07f5edef_7ead5bec :
PS4, Line 274: BusBase
> From what I understand looking that the Intel reference code the PCI domain always covers all busses. Can you confirm that?
> Isn't the CXL PCI device on bus BusBase just a regular PCI bridge?

The ACPI code suggests it needs 2 root bridges so I would think the CXL devices are not enumeratable from a bridge on BusBase?