Patch set updated for coreboot: src/southbridge/amd/sr5650: Always configure lane director on startup

[Timothy Pearson]

Timothy Pearson ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12014

-gerrit

commit daed610c48b0720ec8b5b2afb719b3247675708d
Author: Timothy Pearson 
Date:   Fri Jul 3 17:16:22 2015 -0500

src/southbridge/amd/sr5650: Always configure lane director on startup

On the ASUS KGPE-D16 it was noted that the pin straps did not properly
    configure the lane director hardware, causing link training failure
    on NIC B.  Forcing coreboot to always reconfigure the lane director
    on startup resolves this problem.

Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad
    Signed-off-by: Timothy Pearson 
---
 src/southbridge/amd/sr5650/pcie.c | 13 +++----------
 1 file changed, 3 insertions(+), 10 deletions(-)

diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c
index 9114c81..4161c18 100644
--- a/src/southbridge/amd/sr5650/pcie.c
+++ b/src/southbridge/amd/sr5650/pcie.c
@@ -858,8 +858,6 @@ void sr56x0_lock_hwinitreg(void)
 void config_gpp_core(device_t nb_dev, device_t sb_dev)
 {
    u32 reg;
-	struct southbridge_amd_sr5650_config *cfg =
-		(struct southbridge_amd_sr5650_config *)nb_dev->chip_info;

reg = nbmisc_read_index(nb_dev, 0x20);
    if (AtiPcieCfg.Config & PCIE_ENABLE_STATIC_DEV_REMAP)
@@ -875,14 +873,9 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev)
    reg &= ~((1 << 31) | (1 << 15) | (1 << 13));	//De-asserts
    nbmisc_write_index(nb_dev, 0x8, reg);

-	reg = nbmisc_read_index(nb_dev, 0x67); /* get STRAP_BIF_LINK_CONFIG at bit 0-4 */
-	if (cfg->gpp3a_configuration != (reg & 0x1F))
-		switching_gpp3a_configurations(nb_dev, sb_dev);
-	reg = nbmisc_read_index(nb_dev, 0x8);  /* get MULTIPORT_CONFIG_GPP1 MULTIPORT_CONFIG_CONFIG_GPP2 at bit 8,9 */
-	if ((cfg->gpp1_configuration << 8) != (reg & (1 << 8)))
-		switching_gpp1_configurations(nb_dev, sb_dev);
-	if ((cfg->gpp2_configuration << 9) != (reg & (1 << 9)))
-		switching_gpp2_configurations(nb_dev, sb_dev);
+	switching_gpp3a_configurations(nb_dev, sb_dev);
+	switching_gpp1_configurations(nb_dev, sb_dev);
+	switching_gpp2_configurations(nb_dev, sb_dev);
    ValidatePortEn(nb_dev);
 }