Attention is currently required from: Martin L Roth, Varshit Pandya.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82262?usp=email )
Change subject: vc/amd/opensil: introduce common mpio/chip.h header file ......................................................................
vc/amd/opensil: introduce common mpio/chip.h header file
The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account.
I looked into making the path to the actual MPIO chip.h file configurable via a Kconfig setting, but since a Kconfig string is a string and not a C pre-processor token, I wasn't able to use that for the include.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 --- M src/mainboard/amd/onyx_poc/devicetree.cb M src/soc/amd/genoa_poc/chipset.cb M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h A src/vendorcode/amd/opensil/mpio/chip.h M src/vendorcode/amd/opensil/stub/mpio/chip.c M src/vendorcode/amd/opensil/stub/mpio/chip.h 7 files changed, 112 insertions(+), 98 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/82262/1
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index c1b2f5c..08d2f75 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,7 +55,7 @@ device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + chip vendorcode/amd/opensil/mpio # P2 register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" @@ -63,7 +63,7 @@ register "aspm" = "L1" device ref gpp_bridge_0_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + chip vendorcode/amd/opensil/mpio # G2 register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" @@ -72,7 +72,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_0_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" @@ -93,7 +93,7 @@ device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + chip vendorcode/amd/opensil/mpio # P3 register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" @@ -101,7 +101,7 @@ register "aspm" = "L1" device ref gpp_bridge_1_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + chip vendorcode/amd/opensil/mpio # G3 register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" @@ -114,7 +114,7 @@ device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + chip vendorcode/amd/opensil/mpio # P1 register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" @@ -123,7 +123,7 @@ register "hotplug" = "ServerExpress" device ref gpp_bridge_2_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + chip vendorcode/amd/opensil/mpio # G1 register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" @@ -137,7 +137,7 @@ device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + chip vendorcode/amd/opensil/mpio # P0 register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" @@ -145,7 +145,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + chip vendorcode/amd/opensil/mpio # G0 register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" @@ -153,7 +153,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" @@ -161,7 +161,7 @@ register "aspm" = "L1" device ref gpp_bridge_3_0_c on end # WAFL end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" @@ -170,7 +170,7 @@ register "bmc" = "1" device ref gpp_bridge_3_1_c on end # BMC end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" diff --git a/src/soc/amd/genoa_poc/chipset.cb b/src/soc/amd/genoa_poc/chipset.cb index 92dcb5d..2332a4e 100644 --- a/src/soc/amd/genoa_poc/chipset.cb +++ b/src/soc/amd/genoa_poc/chipset.cb @@ -16,78 +16,78 @@ device pci 00.3 alias rcec_0 off end
device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.1 alias gpp_bridge_0_0_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.2 alias gpp_bridge_0_1_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.3 alias gpp_bridge_0_2_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.4 alias gpp_bridge_0_3_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.5 alias gpp_bridge_0_4_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.6 alias gpp_bridge_0_5_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.7 alias gpp_bridge_0_6_a off end end
device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.1 alias gpp_bridge_0_7_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.2 alias gpp_bridge_0_8_a off end end
device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.1 alias gpp_bridge_0_0_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.2 alias gpp_bridge_0_1_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.3 alias gpp_bridge_0_2_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.4 alias gpp_bridge_0_3_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.5 alias gpp_bridge_0_4_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.6 alias gpp_bridge_0_5_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.7 alias gpp_bridge_0_6_b off end end
device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.1 alias gpp_bridge_0_7_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.2 alias gpp_bridge_0_8_b off end end
device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.1 alias gpp_bridge_0_0_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.2 alias gpp_bridge_0_1_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.3 alias gpp_bridge_0_2_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.4 alias gpp_bridge_0_3_c off end end
@@ -128,64 +128,64 @@ device pci 00.3 alias rcec_1 off end
device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.1 alias gpp_bridge_1_0_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.2 alias gpp_bridge_1_1_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.3 alias gpp_bridge_1_2_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.4 alias gpp_bridge_1_3_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.5 alias gpp_bridge_1_4_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.6 alias gpp_bridge_1_5_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.7 alias gpp_bridge_1_6_a off end end
device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.1 alias gpp_bridge_1_7_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.2 alias gpp_bridge_1_8_a off end end
device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.1 alias gpp_bridge_1_0_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.2 alias gpp_bridge_1_1_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.3 alias gpp_bridge_1_2_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.4 alias gpp_bridge_1_3_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.5 alias gpp_bridge_1_4_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.6 alias gpp_bridge_1_5_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.7 alias gpp_bridge_1_6_b off end end
device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.1 alias gpp_bridge_1_7_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.2 alias gpp_bridge_1_8_b off end end
@@ -207,64 +207,64 @@ device pci 00.3 alias rcec_2 off end
device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.1 alias gpp_bridge_2_0_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.2 alias gpp_bridge_2_1_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.3 alias gpp_bridge_2_2_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.4 alias gpp_bridge_2_3_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.5 alias gpp_bridge_2_4_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.6 alias gpp_bridge_2_5_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.7 alias gpp_bridge_2_6_a off end end
device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.1 alias gpp_bridge_2_7_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.2 alias gpp_bridge_2_8_a off end end
device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.1 alias gpp_bridge_2_0_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.2 alias gpp_bridge_2_1_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.3 alias gpp_bridge_2_2_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.4 alias gpp_bridge_2_3_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.5 alias gpp_bridge_2_4_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.6 alias gpp_bridge_2_5_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.7 alias gpp_bridge_2_6_b off end end
device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.1 alias gpp_bridge_2_7_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.2 alias gpp_bridge_2_8_b off end end
@@ -286,78 +286,78 @@ device pci 00.3 alias rcec_3 off end
device pci 01.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.1 alias gpp_bridge_3_0_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.2 alias gpp_bridge_3_1_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.3 alias gpp_bridge_3_2_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.4 alias gpp_bridge_3_3_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.5 alias gpp_bridge_3_4_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.6 alias gpp_bridge_3_5_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 01.7 alias gpp_bridge_3_6_a off end end
device pci 02.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.1 alias gpp_bridge_3_7_a off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 02.2 alias gpp_bridge_3_8_a off end end
device pci 03.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.1 alias gpp_bridge_3_0_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.2 alias gpp_bridge_3_1_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.3 alias gpp_bridge_3_2_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.4 alias gpp_bridge_3_3_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.5 alias gpp_bridge_3_4_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.6 alias gpp_bridge_3_5_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 03.7 alias gpp_bridge_3_6_b off end end
device pci 04.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.1 alias gpp_bridge_3_7_b off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 04.2 alias gpp_bridge_3_8_b off end end
device pci 05.0 on end # Dummy device function, do not disable - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.1 alias gpp_bridge_3_0_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.2 alias gpp_bridge_3_1_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.3 alias gpp_bridge_3_2_c off end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/mpio device pci 05.4 alias gpp_bridge_3_3_c off end end
diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 089096f..e3ed60e 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -9,7 +9,7 @@ #include "chip.h" #include "../opensil.h"
-struct chip_operations vendorcode_amd_opensil_genoa_poc_mpio_ops = { +struct chip_operations vendorcode_amd_opensil_mpio_ops = { .name = "AMD GENOA MPIO", };
@@ -130,7 +130,7 @@ static uint32_t slot_num; const uint32_t domain = dev->upstream->dev->path.domain.domain; const uint32_t devfn = dev->path.pci.devfn; - const struct vendorcode_amd_opensil_genoa_poc_mpio_config *const config = dev->chip_info; + const struct vendorcode_amd_opensil_mpio_config *const config = dev->chip_info; printk(BIOS_DEBUG, "Setting MPIO port for domain 0x%x, PCI %d:%d\n", domain, PCI_SLOT(devfn), PCI_FUNC(devfn));
@@ -199,7 +199,7 @@
/* Find all devices with this chip that are directly below the chip */ for (struct device *dev = &dev_root; dev; dev = dev->next) - if (dev->chip_ops == &vendorcode_amd_opensil_genoa_poc_mpio_ops && + if (dev->chip_ops == &vendorcode_amd_opensil_mpio_ops && dev->chip_info != dev->upstream->dev->chip_info) per_device_config(mpio_data, dev); } diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 36d6baf..d7b5313 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -54,7 +54,7 @@ L0sL1, };
-struct vendorcode_amd_opensil_genoa_poc_mpio_config { +struct vendorcode_amd_opensil_mpio_config { enum mpio_type type; uint8_t start_lane; uint8_t end_lane; diff --git a/src/vendorcode/amd/opensil/mpio/chip.h b/src/vendorcode/amd/opensil/mpio/chip.h new file mode 100644 index 0000000..c869ca6 --- /dev/null +++ b/src/vendorcode/amd/opensil/mpio/chip.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef OPENSIL_MPIO_CHIP_H +#define OPENSIL_MPIO_CHIP_H + +#if CONFIG(SOC_AMD_OPENSIL_STUB) + #include "../stub/mpio/chip.h" +#elif CONFIG(SOC_AMD_OPENSIL_GENOA_POC) + #include "../genoa_poc/mpio/chip.h" +#else + /* TODO: include header file from site-local */ +#endif + +#endif /* OPENSIL_MPIO_CHIP_H */ diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.c b/src/vendorcode/amd/opensil/stub/mpio/chip.c index 895814d..40e9579 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.c +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.c @@ -3,6 +3,6 @@ #include <device/device.h> #include "chip.h"
-struct chip_operations vendorcode_amd_opensil_stub_mpio_ops = { +struct chip_operations vendorcode_amd_opensil_mpio_ops = { .name = "AMD openSIL stub MPIO", }; diff --git a/src/vendorcode/amd/opensil/stub/mpio/chip.h b/src/vendorcode/amd/opensil/stub/mpio/chip.h index 0957ff0..cff2919 100644 --- a/src/vendorcode/amd/opensil/stub/mpio/chip.h +++ b/src/vendorcode/amd/opensil/stub/mpio/chip.h @@ -60,7 +60,7 @@ SLOT_POWER_LIMIT_DIVISOR_1000 = 3, /* Scale factor 0.001 */ };
-struct vendorcode_amd_opensil_stub_mpio_config { +struct vendorcode_amd_opensil_mpio_config { enum mpio_engine_type type; uint8_t start_lane; uint8_t end_lane;
-
Felix Held (Code Review)