Attention is currently required from: Jamie Ryu, Jayvik Desai, Subrata Banik, Wonkyu Kim, Zhixing Ma.
Jérémy Compostella has posted comments on this change by Jamie Ryu. ( https://review.coreboot.org/c/coreboot/+/87035?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/intel/ptlrvp: Update flashmap to allocate 14MB to BIOS ......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/87035/comment/5b516b96_8b5ac5fd?usp... : PS2, Line 9: This updates flashmap descriptor to allocate 18MB to SI_ME : and 14MB for BIOS. PTL RVP coreboot is used with several types of RVP boards and this layout with 14MB BIOS is very convenient for debugging and creating coreboot for certain use cases and tests purpose. This updates the Flashmap (FMAP) descriptor to allocate 18MB to Silicon Management Engine (SI_ME) and 14MB for BIOS. Panther Lake (PTL) Reference Validation Platform (RVP) coreboot is used with several types of RVP boards, and this layout with a 14MB BIOS is very convenient for debugging and creating coreboot for certain use cases and testing purposes.
https://review.coreboot.org/c/coreboot/+/87035/comment/e9f6cb3a_d903defb?usp... : PS2, Line 12: Build the ptlrvp variant(ES) and check flashmap of the coreboot : is updated correctly. TEST=Build the ptlrvp variant (ES) and check if the flashmap of the coreboot is updated correctly.
File src/mainboard/intel/ptlrvp/chromeos.fmd:
https://review.coreboot.org/c/coreboot/+/87035/comment/fbded3d8_0730dbe9?usp... : PS2, Line 14: # This section starts at the 16M boundary in SPI flash. : # PTL does not support a region crossing this boundary, : # because the SPI flash is memory-mapped into two non- : # contiguous windows. Is this still correct ? It looks like SI_ME_PAD starts at 16 MB. So RW_SECTION_B cannot be at 16 MB.
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Jérémy Compostella (Code Review)