Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31287
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
riscv: Use correct argument in a1 when invoking payload
Fix a bug introduced by 31179. Put fdt into a1 correctly.
Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 --- M src/arch/riscv/payload.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31287/1
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 8a07ff8..f3ed5a4 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -44,7 +44,7 @@ write_csr(mepc, doit); asm volatile( "mv a0, %0\n\t" - "mv a1, %0\n\t" + "mv a1, %1\n\t" "mret" ::"r"(hart_id), "r"(fdt) : "a0", "a1");
Hello ron minnich, Jonathan Neuschäfer, build bot (Jenkins), Xiang Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31287
to look at the new patch set (#2).
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
riscv: Use correct argument in a1 when invoking payload
Fix a bug introduced by 31179. Put fdt into a1 correctly.
Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 Signed-off-by: Philipp Hug philipp@hug.cx --- M src/arch/riscv/payload.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31287/2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31287 )
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31287/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31287/2//COMMIT_MSG@9 PS2, Line 9: 31179 Please use the commit hash and summary.
Hello ron minnich, Jonathan Neuschäfer, build bot (Jenkins), Xiang Wang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31287
to look at the new patch set (#3).
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
riscv: Use correct argument in a1 when invoking payload
Fix a bug introduced by: 820dcfceb3901dbb00bb90c876e374126ca14e20 riscv: Simplify payload handling
Put fdt into a1 correctly.
Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 Signed-off-by: Philipp Hug philipp@hug.cx --- M src/arch/riscv/payload.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/31287/3
ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31287 )
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
Patch Set 3: Code-Review+2
ron minnich has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31287 )
Change subject: riscv: Use correct argument in a1 when invoking payload ......................................................................
riscv: Use correct argument in a1 when invoking payload
Fix a bug introduced by: 820dcfceb3901dbb00bb90c876e374126ca14e20 riscv: Simplify payload handling
Put fdt into a1 correctly.
Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159 Signed-off-by: Philipp Hug philipp@hug.cx Reviewed-on: https://review.coreboot.org/c/31287 Reviewed-by: ron minnich rminnich@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/arch/riscv/payload.c 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified ron minnich: Looks good to me, approved
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 8a07ff8..f3ed5a4 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -44,7 +44,7 @@ write_csr(mepc, doit); asm volatile( "mv a0, %0\n\t" - "mv a1, %0\n\t" + "mv a1, %1\n\t" "mret" ::"r"(hart_id), "r"(fdt) : "a0", "a1");
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Paul Menzel (Code Review) -
Philipp Hug (Code Review)
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ron minnich (Code Review)