Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
According to the schematic,SRCCLKREQ1# is not connected, so disable it on voxel.
BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46612/1
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b..e8be8e3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ .tdp_pl4 = 105, }"
+ # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
Patch Set 1: Code-Review+1
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG@9 PS1, Line 9: According to the schematic,SRCCLKREQ1# is not connected, : so disable it on voxel. Reflow for 72 chars wide, please
Hello build bot (Jenkins), Caveh Jalali, Tim Wawrzynczak, Nick Vaccaro, Paul Fagerburg, Derek Huang, YH Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46612
to look at the new patch set (#2).
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel.
BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/46612/2
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG@9 PS1, Line 9: According to the schematic,SRCCLKREQ1# is not connected, : so disable it on voxel.
Reflow for 72 chars wide, please
done, thanks
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
Patch Set 2: Code-Review+2
Sheng-Liang Pan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/46612/1//COMMIT_MSG@9 PS1, Line 9: According to the schematic,SRCCLKREQ1# is not connected, : so disable it on voxel.
done, thanks
Done
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46612 )
Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1# ......................................................................
mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
According to the schematic,SRCCLKREQ1# is not connected,so disable it on voxel.
BUG=b:171279034 BRANCH=volteer TEST="emerge-volteer coreboot" compiles successfully.
Signed-off-by: Pan Sheng-Liang sheng-liang.pan@quanta.corp-partner.google.com Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612 Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Sheng-Liang Pan: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index d7a265b..e8be8e3 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -14,6 +14,9 @@ .tdp_pl4 = 105, }"
+ # Disable SRCCLKREQ1# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + device domain 0 on device ref dptf on chip drivers/intel/dptf
-
Patrick Georgi (Code Review) -
Sheng-Liang Pan (Code Review)
-
Tim Wawrzynczak (Code Review)