John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
device/pci_id: Add Tiger Lake TCSS device ID
Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID.
BUG=None TEST=Built and booted image sucessfully.
Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Signed-off-by: John Zhao john.zhao@intel.com --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/40693/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3de67ca..a42d61f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3537,6 +3537,8 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded
@@ -3647,6 +3649,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/40693
to look at the new patch set (#3).
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
device/pci_id: Add Tiger Lake TCSS device ID
Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID.
BUG=None TEST=Built and booted image sucessfully.
Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Signed-off-by: John Zhao john.zhao@intel.com --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/40693/3
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
Patch Set 3: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... PS3, Line 3540: 0x9a13 Table 11-3 in the 575681-tgl-eds-vol2a-rev1p2.pdf document shows XHCI device ID to be 8C31h.
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... PS3, Line 3626: 0x9a15 Section 11.4.2 in the 575681-tgl-eds-vol2a-rev1p2.pdf document shows XDCI device ID to be 0AAAh.
Am I looking up the wrong device IDs in the eds?
John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
Patch Set 3:
(2 comments)
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... PS3, Line 3540: 0x9a13
Table 11-3 in the 575681-tgl-eds-vol2a-rev1p2.pdf document shows XHCI device ID to be 8C31h.
Table 15-4 in the 57683_tgl_eds-vol1_addendum_rev0p9.pdf shows xhci device ID to be 9a13h. It can be verified "lspci -xxx -s 00:0d.0" after booting to kernel.
https://review.coreboot.org/c/coreboot/+/40693/3/src/include/device/pci_ids.... PS3, Line 3626: 0x9a15
Section 11.4.2 in the 575681-tgl-eds-vol2a-rev1p2.pdf document shows XDCI device ID to be 0AAAh. […]
Table 15-4 in the 57683_tgl_eds-vol1_addendum_rev0p9.pdf shows xdci device ID to be 9a15h. It can be verified "lspci -xxx -s 00:0d.1" after enabling xdci and booting to kernel.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
Patch Set 3: Code-Review+2
Duncan Laurie has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
device/pci_id: Add Tiger Lake TCSS device ID
Add Tiger Lake TCSS USB xHCI, xDCI and Thunderbolt DMA device ID.
BUG=None TEST=Built and booted image sucessfully.
Change-Id: Idef3850666c9f393181e0a13974b9ad79ba258ad Signed-off-by: John Zhao john.zhao@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/40693 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/include/device/pci_ids.h 1 file changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Caveh Jalali: Looks good to me, but someone else must approve
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index cfdcab3..4b17567 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3559,6 +3559,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed #define PCI_DEVICE_ID_INTEL_CMP_H_XHCI 0x06ed #define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XHCI 0x9a13 #define PCI_DEVICE_ID_INTEL_MCC_XHCI 0x4b7d #define PCI_DEVICE_ID_INTEL_JSP_XHCI 0x4ded
@@ -3644,6 +3645,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee #define PCI_DEVICE_ID_INTEL_CMP_H_XDCI 0x06ee #define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee +#define PCI_DEVICE_ID_INTEL_TGP_TCSS_XDCI 0x9a15 #define PCI_DEVICE_ID_INTEL_MCC_XDCI 0x4b7e #define PCI_DEVICE_ID_INTEL_JSP_XDCI 0x4dee
@@ -3669,6 +3671,8 @@ #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP1 0x9a25 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP2 0x9a27 #define PCI_DEVICE_ID_INTEL_TGL_TBT_RP3 0x9a29 +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0 0x9a1b +#define PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1 0x9a1d
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40693 )
Change subject: device/pci_id: Add Tiger Lake TCSS device ID ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/2884 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2883 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/2882 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/2881
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Caveh Jalali (Code Review)
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Duncan Laurie (Code Review)
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John Zhao (Code Review)
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Nick Vaccaro (Code Review)