Change in coreboot[master]: mb/intel/sm: Enable TCSS

[Deepti Deshatty (Code Review)]

Deepti Deshatty has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54091 )

Change subject: mb/intel/sm: Enable TCSS
......................................................................

mb/intel/sm: Enable TCSS

Enable flag SOC_INTEL_COMMON_BLOCK_TCSS.
Add 'mainboard_tcss_get_port_info' function similar to volteer.

TEST=Verified build for shadowmountain

Signed-off-by: Deepti Deshatty 
Change-Id: I8be796295a900bed58b5c7ed6c2300fe504d58a3
---
M src/mainboard/intel/shadowmountain/Kconfig
M src/mainboard/intel/shadowmountain/mainboard.c
2 files changed, 63 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/54091/1

diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 94a279f..b66b054 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -25,6 +25,7 @@
    select PCIEXP_HOTPLUG
    select SOC_INTEL_ALDERLAKE
    select SOC_INTEL_CSE_LITE_SKU
+	select SOC_INTEL_COMMON_BLOCK_TCSS

config CHROMEOS
    select GBB_FLAG_FORCE_DEV_SWITCH_ON
diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c
index 2783b4d..eca29b7 100644
--- a/src/mainboard/intel/shadowmountain/mainboard.c
+++ b/src/mainboard/intel/shadowmountain/mainboard.c
@@ -6,6 +6,68 @@
 #include <ec/ec.h>
 #include <soc/gpio.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include <intelblocks/tcss.h>
+#include <soc/pci_devs.h>
+#include "drivers/intel/pmc_mux/conn/chip.h"
+
+extern struct chip_operations drivers_intel_pmc_mux_conn_ops;
+
+static bool is_correct_port(const struct device *dev, int port)
+{
+	return dev->path.type == DEVICE_PATH_GENERIC && dev->path.generic.id == port
+		&& dev->chip_ops == &drivers_intel_pmc_mux_conn_ops;
+}
+
+static const struct drivers_intel_pmc_mux_conn_config *get_connector_config(
+							const struct device *mux,
+							int port)
+{
+	const struct drivers_intel_pmc_mux_conn_config *config = NULL;
+	DEVTREE_CONST struct device *conn = NULL;
+
+	while ((conn = dev_bus_each_child(mux->link_list, conn)) != NULL) {
+		if (is_correct_port(conn, port))
+			break;
+	}
+
+	if (conn)
+		config = (const struct drivers_intel_pmc_mux_conn_config *) conn->chip_info;
+
+	return config;
+}
+
+const struct tcss_port_map *mainboard_tcss_get_port_info(size_t *num_ports)
+{
+	static struct tcss_port_map port_map[MAX_TYPE_C_PORTS];
+	size_t port;
+	const struct device *pmc;
+	const struct device *mux;
+	const struct drivers_intel_pmc_mux_conn_config *mux_config;
+	size_t active_ports = 0;
+
+	pmc = pcidev_path_on_root(PCH_DEVFN_PMC);
+	if (!pmc || !pmc->link_list) {
+		printk(BIOS_ERR, "%s: unable to find PMC device or its mux\n", __func__);
+		return NULL;
+	}
+
+	mux = pmc->link_list->children;
+	if (!mux)
+		return NULL;
+
+	for (port = 0; port < MAX_TYPE_C_PORTS; port++) {
+		mux_config = get_connector_config(mux, port);
+		if (mux_config == NULL)
+			continue;
+
+		port_map[active_ports].usb2_port = mux_config->usb2_port_number;
+		port_map[active_ports].usb3_port = mux_config->usb3_port_number;
+		active_ports++;
+	}
+
+	*num_ports = active_ports;
+	return port_map;
+}

static void mainboard_init(void *chip_info)
 {