Change in coreboot[master]: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification
Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49012 )
Change subject: soc/intel/jasperlake: Enable USB2 PHY SUS PG for s0ix qualification ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/c/coreboot/+/49012/3//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/49012/3//COMMIT_MSG@10 PS3, Line 10: USB is not power gated
"USB PHY SUS well" since there are more than one qualification bits for USB. […]
This is for USB2.
https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/fi... File src/soc/intel/jasperlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/fi... PS3, Line 69: *
Can you please add a comment here indicating why this is required? It will be helpful when someone l […]
Done
https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/in... File src/soc/intel/jasperlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/in... PS3, Line 125:
Use space like other entries here.
Done
https://review.coreboot.org/c/coreboot/+/49012/3/src/soc/intel/jasperlake/in... PS3, Line 126:
Use space like other entries and align like XTALSDQDIS above.
Done
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Krishna P Bhat D (Code Review)