Hello Marshall Dawson, Marshall Dawson,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/41625
to review the following change.
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
soc/amd/picasso: Add generic SMU service request
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices.
The index/data pair is used access a command register, a response, and six argument values.
BUG=b:153264473 TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/smu.h A src/soc/amd/picasso/smu.c 3 files changed, 112 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41625/1
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index e1416bc..7ca8d9e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -72,6 +72,7 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c +smm-y += smu.c smm-y += config.c
CPPFLAGS_common += -I$(src)/soc/amd/picasso diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h new file mode 100644 index 0000000..2c429b5 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_SMU_H__ +#define __PICASSO_SMU_H__ + +/* SMU registers accessed indirectly using an index/data pair in D0F00 */ +#define SMU_INDEX_ADDR 0xb8 +#define SMU_DATA_ADDR 0xbc + +#define REG_ADDR_MESG_ID 0x3b10528 +#define REG_ADDR_MESG_RESP 0x3b10564 +#define REG_ADDR_MESG_ARGS_BASE 0x0b10998 + +/* Argument 0-5 indexed locations are contiguous */ +#define NUM_ARGS 6 +#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0xc, +}; + +struct smu_payload { + uint32_t msg[NUM_ARGS]; +}; + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if + * any, is returned via arg. Returns 0 if success or -1 on failure. + */ +int send_smu_message(enum smu_message_id id, struct smu_payload *arg); + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines + * S-State and SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* __PICASSO_SMU_H__ */ diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c new file mode 100644 index 0000000..2150f49 --- /dev/null +++ b/src/soc/amd/picasso/smu.c @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <soc/smu.h> + +static uint32_t smu_read32(uint32_t reg) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); +} + +static void smu_write32(uint32_t reg, uint32_t val) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); +} + +static int smu_poll_response(void) +{ + struct stopwatch sw; + const long timeout_ms = 10 * MSECS_PER_SEC; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + if (!smu_read32(REG_ADDR_MESG_RESP)) { + printk(BIOS_SPEW, "SMU command consumed %ld msecs\n", + stopwatch_duration_usecs(&sw)); + return 0; + } + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + return -1; +} + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if + * any, is returned via arg. Returns 0 if success or -1 on failure. + */ +int send_smu_message(enum smu_message_id id, struct smu_payload *arg) +{ + int i; + + smu_write32(REG_ADDR_MESG_RESP, 0); + + for (i = 0 ; i < NUM_ARGS ; i++) + smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); + + smu_write32(REG_ADDR_MESG_ID, id); + if (smu_poll_response()) + return -1; + + for (i = 0 ; i < NUM_ARGS ; i++) + arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); + + return 0; +} + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines + * S-State and SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void) +{ + struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ + + printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); + send_smu_message(SMC_MSG_S3ENTRY, &msg); +}
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@2... PS1, Line 21: smu_poll_response Can you make this return the response value..
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 47: The PPR says: 1. Wait until the Response register is non-zero. 2. Write zero (0) to the Response register.
Do we need to add the first wait?
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@5... PS1, Line 56: Check the response value:
- If the Response register contains OK, then the SMU has finished processing the message.
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 1: Code-Review-1
will look into that as soon as I have mandolin working again on top of current upstream master
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 1:
(1 comment)
I'm reworking this patch right now
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@2... PS1, Line 29: if (!smu_read32(REG_ADDR_MESG_RESP)) { this is very likely wrong; should probably be if (smu_read32(REG_ADDR_MESG_RESP))
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41625
to look at the new patch set (#2).
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
soc/amd/picasso: Add generic SMU service request
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices.
The index/data pair is used access a command register, a response, and six argument values.
BUG=b:153264473 TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/smu.h A src/soc/amd/picasso/smu.c 3 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41625/2
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 2:
(4 comments)
still needs to be tested on real hardware
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@2... PS1, Line 21: smu_poll_response
Can you make this return the response value..
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@2... PS1, Line 29: if (!smu_read32(REG_ADDR_MESG_RESP)) {
this is very likely wrong; should probably be if (smu_read32(REG_ADDR_MESG_RESP))
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 47:
The PPR says: […]
Not sure if that's really needed in practice, but I've added it
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@5... PS1, Line 56:
Check the response value: […]
Done
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41625/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41625/1//COMMIT_MSG@13 PS1, Line 13: used used to
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... File src/soc/amd/picasso/include/soc/smu.h:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... PS1, Line 30: int Use CB_SUCCESS and friends?
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... PS1, Line 33: put to put
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 46: int unsigned
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Marshall Dawson,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41625
to look at the new patch set (#3).
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
soc/amd/picasso: Add generic SMU service request
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices.
The index/data pair is used to access a command register, a response, and six argument values.
BUG=b:153264473 TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/smu.h A src/soc/amd/picasso/smu.c 3 files changed, 129 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41625/3
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41625/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/41625/1//COMMIT_MSG@13 PS1, Line 13: used
used to
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... File src/soc/amd/picasso/include/soc/smu.h:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... PS1, Line 30: int
Use CB_SUCCESS and friends?
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/include... PS1, Line 33: put
to put
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 46: int
unsigned
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41625/3/src/soc/amd/picasso/include... File src/soc/amd/picasso/include/soc/smu.h:
https://review.coreboot.org/c/coreboot/+/41625/3/src/soc/amd/picasso/include... PS3, Line 23: uint32_t #include header that defines types you use. cb_err is below as well.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 3: Code-Review+1
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Furquan Shaikh, Patrick Georgi, Martin Roth, Marshall Dawson, Marshall Dawson, Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41625
to look at the new patch set (#4).
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
soc/amd/picasso: Add generic SMU service request
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices.
The index/data pair is used to access a command register, a response, and six argument values.
BUG=b:153264473 TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh furquan@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/smu.h A src/soc/amd/picasso/smu.c 3 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/41625/4
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41625/3/src/soc/amd/picasso/include... File src/soc/amd/picasso/include/soc/smu.h:
https://review.coreboot.org/c/coreboot/+/41625/3/src/soc/amd/picasso/include... PS3, Line 23: uint32_t
#include header that defines types you use. cb_err is below as well.
Done
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 47:
Not sure if that's really needed in practice, but I've added it
i'd say that it's done, but needs to be tested, so i leave this one open until it's tested again
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 4: Code-Review+2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/41625/4/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/4/src/soc/amd/picasso/smu.c@3... PS4, Line 38: usecs This is usecs, the comment says msecs.
When I tried this I saw the following:
SMI#: Entering S3 (Suspend-To-RAM) PSP: Prepare to enter sleep state 3... OK SMU: Put system into S3/S4/S5 SMU command consumed 1 msecs
So is this saying the PSP command completed in 1 us? Seems a little fast doesn't it?
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/1/src/soc/amd/picasso/smu.c@4... PS1, Line 47:
i'd say that it's done, but needs to be tested, so i leave this one open until it's tested again
Done
https://review.coreboot.org/c/coreboot/+/41625/4/src/soc/amd/picasso/smu.c File src/soc/amd/picasso/smu.c:
https://review.coreboot.org/c/coreboot/+/41625/4/src/soc/amd/picasso/smu.c@3... PS4, Line 38: usecs
This is usecs, the comment says msecs. […]
that's from the first revision of the patch where this function was only used after the smu_write32(REG_ADDR_MESG_ID, id) call. I'll fix this in a follow-up. So the 1us is the one check if the SMU is ready to accept a new command. In the case of the SMC_MSG_S3ENTRY command, the x86 cores are stopped shortly after the smu_write32(REG_ADDR_MESG_ID, id) call, so the second time the message won't get printed
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 4: Code-Review+2
Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
soc/amd/picasso: Add generic SMU service request
Add a new feature that allows messages to be sent to the SMU. The offsets of the PCI config index/data indirect registers have been documented for prior generation devices.
The index/data pair is used to access a command register, a response, and six argument values.
BUG=b:153264473 TEST=Verify service can be used to take the system into S3
Change-Id: Ide431aa976cb2f8bdc248cb08aa0724a9596ac5a Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Signed-off-by: Felix Held felix-coreboot@felixheld.de Reviewed-on: https://chromium-review.googlesource.com/2161796 Reviewed-by: Furquan Shaikh furquan@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/41625 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/include/soc/smu.h A src/soc/amd/picasso/smu.c 3 files changed, 131 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 05d46ea..d0046ea 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -72,6 +72,7 @@ smm-$(CONFIG_DEBUG_SMI) += uart.c smm-y += gpio.c smm-y += psp.c +smm-y += smu.c smm-y += config.c
CPPFLAGS_common += -I$(src)/soc/amd/picasso diff --git a/src/soc/amd/picasso/include/soc/smu.h b/src/soc/amd/picasso/include/soc/smu.h new file mode 100644 index 0000000..128f4c4 --- /dev/null +++ b/src/soc/amd/picasso/include/soc/smu.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __PICASSO_SMU_H__ +#define __PICASSO_SMU_H__ + +#include <types.h> + +/* SMU registers accessed indirectly using an index/data pair in D0F00 config space */ +#define SMU_INDEX_ADDR 0xb8 /* 32 bit */ +#define SMU_DATA_ADDR 0xbc /* 32 bit */ + +#define REG_ADDR_MESG_ID 0x3b10528 +#define REG_ADDR_MESG_RESP 0x3b10564 +#define REG_ADDR_MESG_ARGS_BASE 0x0b10998 + +/* Argument 0-5 indexed locations are contiguous */ +#define SMU_NUM_ARGS 6 +#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t))) + +enum smu_message_id { + SMC_MSG_S3ENTRY = 0x0c, +}; + +struct smu_payload { + uint32_t msg[SMU_NUM_ARGS]; +}; + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if + * any, is returned via arg. Returns 0 if success or -1 on failure. + */ +enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg); + +/* + * Request the SMU put system into S3, S4, or S5. On entry, SlpTyp determines + * S-State and SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void); + +#endif /* __PICASSO_SMU_H__ */ diff --git a/src/soc/amd/picasso/smu.c b/src/soc/amd/picasso/smu.c new file mode 100644 index 0000000..cfe2240 --- /dev/null +++ b/src/soc/amd/picasso/smu.c @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <timer.h> +#include <console/console.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <soc/smu.h> +#include <types.h> + +static uint32_t smu_read32(uint32_t reg) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + return pci_read_config32(SOC_GNB_DEV, SMU_DATA_ADDR); +} + +static void smu_write32(uint32_t reg, uint32_t val) +{ + pci_write_config32(SOC_GNB_DEV, SMU_INDEX_ADDR, reg); + pci_write_config32(SOC_GNB_DEV, SMU_DATA_ADDR, val); +} + +#define SMU_MESG_RESP_TIMEOUT 0x00 +#define SMU_MESG_RESP_OK 0x01 + +/* returns SMU_MESG_RESP_OK, SMU_MESG_RESP_TIMEOUT or a negative number */ +static int32_t smu_poll_response(void) +{ + struct stopwatch sw; + const long timeout_ms = 10 * MSECS_PER_SEC; + int32_t result; + + stopwatch_init_msecs_expire(&sw, timeout_ms); + + do { + result = smu_read32(REG_ADDR_MESG_RESP); + if (result) { + printk(BIOS_SPEW, "SMU command consumed %ld msecs\n", + stopwatch_duration_usecs(&sw)); + return result; + } + } while (!stopwatch_expired(&sw)); + + printk(BIOS_ERR, "Error: timeout sending SMU message\n"); + return SMU_MESG_RESP_TIMEOUT; +} + +/* + * Send a message and bi-directional payload to the SMU. SMU response, if any, is returned via + * arg. + */ +enum cb_err send_smu_message(enum smu_message_id id, struct smu_payload *arg) +{ + size_t i; + + /* wait until SMU can process a new request; don't care if an old request failed */ + if (smu_poll_response() == SMU_MESG_RESP_TIMEOUT) + return CB_ERR; + + /* clear response register */ + smu_write32(REG_ADDR_MESG_RESP, 0); + + /* populate arguments */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + smu_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]); + + /* send message to SMU */ + smu_write32(REG_ADDR_MESG_ID, id); + + /* wait until SMU has processed the message and check if it was successful */ + if (smu_poll_response() != SMU_MESG_RESP_OK) + return CB_ERR; + + /* copy returned values */ + for (i = 0 ; i < SMU_NUM_ARGS ; i++) + arg->msg[i] = smu_read32(REG_ADDR_MESG_ARG(i)); + + return CB_SUCCESS; +} + +/* + * Request the SMU to put system into S3, S4, or S5. On entry, SlpTyp determines S-State and + * SlpTypeEn is clear. Function does not return if successful. + */ +void smu_sx_entry(void) +{ + struct smu_payload msg = { 0 }; /* Unused for SMC_MSG_S3ENTRY */ + + printk(BIOS_DEBUG, "SMU: Put system into S3/S4/S5\n"); + send_smu_message(SMC_MSG_S3ENTRY, &msg); +}
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41625 )
Change subject: soc/amd/picasso: Add generic SMU service request ......................................................................
Patch Set 5:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4226 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4225 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4224 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4223
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Aaron Durbin (Code Review)
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Angel Pons (Code Review)
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Felix Held (Code Review)
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Paul Menzel (Code Review)
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Raul Rangel (Code Review)