Change in ...coreboot[master]: mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32181
Change subject: mb/mainboard/google/sarien/variants: Set correct tcc_offset value ......................................................................
mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32181/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bf3736..1507214 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -161,7 +161,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "5" + register "tcc_offset" = "10"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index caae79f..79329d5 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -158,7 +158,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "5" + register "tcc_offset" = "10"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32181 )
Change subject: mb/mainboard/google/sarien/variants: Set correct tcc_offset value ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32181 )
Change subject: mb/mainboard/google/sarien/variants: Set correct tcc_offset value ......................................................................
mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Set new tcc_offset value to 10 degree C. This configures the Thermal Control Circuit (TCC) activation value to 90 degree C. It prevents any abrupt thermal shutdown while running heavy workload. This helps to take early thermal throttling action when CPU temperature goes above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 4bf3736..1507214 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -161,7 +161,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "5" + register "tcc_offset" = "10"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f04149f..e4a92a9 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -158,7 +158,7 @@ #| I2C4 | H1 TPM | #+-------------------+---------------------------+
- register "tcc_offset" = "5" + register "tcc_offset" = "10"
register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
-
Furquan Shaikh (Code Review) -
Patrick Georgi (Code Review)
-
Sumeet R Pawnikar (Code Review)