Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50119 )
Change subject: soc/amd: Drop PCNT from GNVS ......................................................................
soc/amd: Drop PCNT from GNVS
It's a static value that is neither referenced from SMI handler nor needs to be updated on S3 resume path.
Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/acpi/cpu.asl M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/include/soc/nvs.h M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/cpu.asl M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 8 files changed, 14 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index ed2be48..ebb2bcd 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -384,6 +384,10 @@
acpigen_pop_len(); } + + acpigen_write_scope("\"); + acpigen_write_name_integer("PCNT", logical_cores); + acpigen_pop_len(); }
unsigned long southbridge_write_acpi_tables(const struct device *device, @@ -398,9 +402,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); }
static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index e1b7498..294d89f 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -36,6 +36,7 @@ * Processor Object */ /* These devices are created at runtime */ +External (\PCNT, IntObj) External (_SB.C000, DeviceObj) External (_SB.C001, DeviceObj) External (_SB.C002, DeviceObj) diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index 9d3f381..31d375c 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -12,7 +12,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - PCNT, 8, // 0x00 - Processor Count + , 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console diff --git a/src/soc/amd/picasso/include/soc/nvs.h b/src/soc/amd/picasso/include/soc/nvs.h index f10fbdd..b8945ff 100644 --- a/src/soc/amd/picasso/include/soc/nvs.h +++ b/src/soc/amd/picasso/include/soc/nvs.h @@ -14,7 +14,7 @@
struct __packed global_nvs { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t lids; /* 0x01 - LID State */ uint8_t pwrs; /* 0x02 - AC Power State */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 19add66..ae2de67 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -152,6 +152,10 @@ acpigen_write_processor(cpu, 0, 0); acpigen_pop_len(); } + + acpigen_write_scope("\"); + acpigen_write_name_integer("PCNT", cores); + acpigen_pop_len(); }
unsigned long southbridge_write_acpi_tables(const struct device *device, @@ -166,9 +170,6 @@ /* Set unknown wake source */ gnvs->pm1i = ~0ULL; gnvs->gpei = ~0ULL; - - /* CPU core count */ - gnvs->pcnt = dev_count_cpu(); }
static void acpigen_soc_get_gpio_in_local5(uintptr_t addr) diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index ca5f249..24b81a1 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -9,6 +9,7 @@ * Processor Object */ /* These devices are created at runtime */ +External (\PCNT, IntObj) External (_SB.P000, DeviceObj) External (_SB.P001, DeviceObj) External (_SB.P002, DeviceObj) diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 7a48dd5..ce3653c 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -9,7 +9,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ - PCNT, 8, // 0x00 - Processor Count + , 8, // 0x00 - Processor Count LIDS, 8, // 0x01 - LID State PWRS, 8, // 0x02 - AC Power State CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index e4a158c..055d74b 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -14,7 +14,7 @@
struct __packed global_nvs { /* Miscellaneous */ - uint8_t pcnt; /* 0x00 - Processor Count */ + uint8_t unused_was_pcnt; /* 0x00 - Processor Count */ uint8_t lids; /* 0x01 - LID State */ uint8_t pwrs; /* 0x02 - AC Power State */ uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */
-
Patrick Georgi (Code Review)