Change in coreboot[master]: soc/mediatek: PCI: Assert PERST# at bootblock stage

[Hung-Te Lin (Code Review)]

Attention is currently required from: Shelley Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang.
Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 )

Change subject: soc/mediatek: PCI: Assert PERST# at bootblock stage
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Patch Set 9:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/62359/comment/f5c8ad23_28cf9375 
PS9, Line 14: 100ms
> a hacky implementation: we can assume the pre-init should be done very early in the bootblock, for e […]

Looking at a typical 8195 boot timeline:

- entire bootblock takes 68ms
- verstage takes 250ms
- romstage takes 210ms

So the ramstage is really unlikely to start less than 100ms. Another trick is maybe we can also save the time execution time of romstage, to the ddrinfo, so it'd be pretty easy to make sure there's enough latency.