Change in coreboot[master]: src/soc/amd/stoneyridge: clean up southbridge.c

[Garrett Kirkendall (Code Review)]

Garrett Kirkendall has uploaded this change for review. ( https://review.coreboot.org/25010

Change subject: src/soc/amd/stoneyridge: clean up southbridge.c
......................................................................

src/soc/amd/stoneyridge: clean up southbridge.c

* Limit dependency on vendorcode header files and use defines from
  iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.

BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt

Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall 
---
M src/soc/amd/stoneyridge/southbridge.c
1 file changed, 38 insertions(+), 25 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25010/1

diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index c1dd516..598150f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -30,7 +30,6 @@
 #include <fchec.h>
 #include <delay.h>
 #include <soc/pci_devs.h>
-#include <agesa_headers.h>

static int is_sata_config(void)
 {
@@ -272,42 +271,56 @@
    return index;
 }

-void configure_stoneyridge_uart(void)
+static void power_on_aoac_device(int aoac_device_control_register)
 {
-	u8 byte, byte2;
-
-	if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1)
-		return;
+	uint8_t byte;

/* Power on the UART and AMBA devices */
-	byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
-					+ CONFIG_UART_FOR_CONSOLE * 2);
+	byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE
+			+ aoac_device_control_register);
    byte |= AOAC_PWR_ON_DEV;
-	write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56
-					+ CONFIG_UART_FOR_CONSOLE * 2, byte);
+	write8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE
+			+ aoac_device_control_register, byte);
+}

-	byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62);
-	byte |= AOAC_PWR_ON_DEV;
-	write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG62, byte);
+static bool is_aoac_device_enabled(int aoac_device_status_register)
+{
+	uint8_t byte;
+	byte = read8((uint8_t *)(uintptr_t)AOAC_MMIO_BASE
+			+ aoac_device_status_register);
+	byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
+	if (byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))
+		return true;
+	else
+		return false;
+}
+
+void configure_stoneyridge_uart(void)
+{
+	bool status;
+
+	/* Power on the UART and AMBA devices */
+	power_on_aoac_device(AOAC_D3_CONTROL_UART0
+			+ CONFIG_UART_FOR_CONSOLE * 2);
+	power_on_aoac_device(AOAC_D3_CONTROL_AMBA);

/* Set the GPIO mux to UART */
-	write8((void *)FCH_IOMUXx89_UART0_RTS_L_EGPIO137, 0);
-	write8((void *)FCH_IOMUXx8A_UART0_TXD_EGPIO138, 0);
-	write8((void *)FCH_IOMUXx8E_UART1_RTS_L_EGPIO142, 0);
-	write8((void *)FCH_IOMUXx8F_UART1_TXD_EGPIO143, 0);
+	write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART0_RTS_L_EGPIO137,
+			UART0_RTS_L);
+	write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART0_TXD_EGPIO138,
+			UART0_TXD);
+	write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART1_RTS_L_EGPIO142,
+			UART1_RTS_L);
+	write8((uint8_t *)(uintptr_t)IOMUX_MMIO_BASE + UART1_TXD_EGPIO143,
+			UART1_TXD);

/* Wait for the UART and AMBA devices to indicate power and clock OK */
    do {
    	udelay(100);
-		byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG57
+		status = is_aoac_device_enabled(AOAC_D3_STATE_UART0
    				+ CONFIG_UART_FOR_CONSOLE * 2);
-		byte &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
-		byte2 = read8((void *)ACPI_MMIO_BASE + AOAC_BASE
-					+ FCH_AOAC_REG63);
-		byte2 &= (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE);
-	} while (!((byte == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE)) &&
-		   (byte2 == (A0AC_PWR_RST_STATE | AOAC_RST_CLK_OK_STATE))));
-
+		status &= is_aoac_device_enabled(AOAC_D3_STATE_AMBA);
+	} while (!status);
 }

void sb_pci_port80(void)