Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports - coreboot-gerrit

18 Aug 2020


      Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 )
Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports
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Patch Set 25:
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Patch Set 25:
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Patch Set 25: Code-Review+1
LGTM. Are there any interdependencies with any of the other PCIe PM-related settings?
Perhaps that "PcieRpAspm" doesn't disable L1 for a given root port?
should coreboot automatically disable L1SS on a given port if PcieRpAspm is disabled for that port? Or are we just depending on the board config to be sane?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8
Gerrit-Change-Number: 39538
Gerrit-PatchSet: 25
Gerrit-Owner: Benjamin Doron benjamin.doron00@gmail.com
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