Change in coreboot[master]: soc/intel/tigerlake: Enable Hybride storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

Enable Hybrid storage auto detection

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index 02855b1..5cd3798 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -262,6 +262,9 @@
    uint8_t DdiPort2Ddc;
    uint8_t DdiPort3Ddc;
    uint8_t DdiPort4Ddc;
+
+	/* Hybrid storage mode enable(1)/disable(0) */
+	uint8_t HybridStorageMode;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index d22cde0..edf07c9 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,9 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* Enable Hybrid storage auto detection */
+	params->HybridStorageMode = config->HybridStorageMode;
+
    /* Legacy 8254 timer support */
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

Enable Hybrid storage auto detection

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/2

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143:         params->HybridStorageMode = config->HybridStorageMode;
code indent should use tabs where possible

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143:         params->HybridStorageMode = config->HybridStorageMode;
please, no spaces at the start of a line

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

Enable Hybrid storage auto detection

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/3

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143:         params->HybridStorageMode = config->HybridStorageMode;
> code indent should use tabs where possible

Ack

https://review.coreboot.org/c/coreboot/+/39232/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 143:         params->HybridStorageMode = config->HybridStorageMode;
> please, no spaces at the start of a line

Ack

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#4).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/4

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 4:

Waiting for UPD header patch for HybridStorageMode

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 4:

(3 comments)

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@8 
PS4, Line 8: 
Describe the problem?
> Currently, only one mode/type can be booted from. Intel Tiger Like
> supports an hybride mode, …

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@11 
PS4, Line 11: form
from

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@12 
PS4, Line 12: Pcie
PCIe

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), caveh jalali, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#5).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

For using hybrid storage(optane), we need to use 2x2 PCIe configuration
while we need to use 1x4 PCIe configuration for NVMe. And this can be
configured by fit configuration which is built time.
By enabling Hybrid Storage mode in FSP, FSP will detect Hybrid storage
and configure PCIe lane accordingly during boot up and save configuration
for next boot up.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP form NVMe and Optane
Check Pcie lane configuration
Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/5

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), caveh jalali, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

For using hybrid storage(optane), we need to use 2x2 PCIe configuration
while we need to use 1x4 PCIe configuration for NVMe. And this can be
configured by fit configuration which is built time.
By enabling Hybrid Storage mode in FSP, FSP will detect Hybrid storage
and configure PCIe lane accordingly during boot up and save configuration
for next boot up.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/6

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 6: Code-Review+1

(3 comments)

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@8 
PS4, Line 8:
> Describe the problem? […]

Ack

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@11 
PS4, Line 11: form
> from

Ack

https://review.coreboot.org/c/coreboot/+/39232/4//COMMIT_MSG@12 
PS4, Line 12: Pcie
> PCIe

Ack

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 6: -Code-Review

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 6:

(4 comments)

Why is this done by the FSP and not in coreboot?

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@9 
PS6, Line 9: storage(optane)
Please add a space before the (.

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@12 
PS6, Line 12: By enabling Hybrid Storage mode in FSP, FSP will detect Hybrid storage
Please add one blank line above to separate paragraphs.

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@12 
PS6, Line 12: FSP
What FSP component is that?

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
PS6, Line 266: 	/* Hybrid storage mode enable(1)/disable(0) */
Please add a space before the (.

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

Patch Set 6:

(7 comments)
> Patch Set 6:
>
> (4 comments)
>
> Why is this done by the FSP and not in coreboot?

FSP sets up the PCIe lanes already, so it just got added there I guess.

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@7 
PS6, Line 7: Hybride
remove the `e` at the end: Hybrid

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@9 
PS6, Line 9: For using
To use

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@9 
PS6, Line 9: storage(optane)
> Please add a space before the (.

I think `Optane` should be capitalized as well

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@10 
PS6, Line 10: And this can be
            : configured by fit configuration which is built time.
There are lots of words related to `configure` close together. How about rewriting this sentence as:

The mode can be selected using the FIT tool at build time.

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@12 
PS6, Line 12: FSP
> What FSP component is that?

FSP-S

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@13 
PS6, Line 13: and save configuration
            : for next boot up.
Where does it get saved to? Also, to avoid repeating `configure`, I would use:

... and save the settings for the next boot.

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
PS6, Line 266: 	/* Hybrid storage mode enable(1)/disable(0) */
> Please add a space before the (.

It would be inconsistent with the comments above, though...

I would mention that this is about Optane/NVMe

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), caveh jalali, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Enable Hybride storage mode
......................................................................

soc/intel/tigerlake: Enable Hybride storage mode

For using hybrid storage(optane), we need to use 2x2 PCIe configuration
while we need to use 1x4 PCIe configuration for NVMe. And this can be
configured by fit configuration which is built time.
By enabling Hybrid Storage mode in FSP, FSP will configure 2x2 PCIe
configuration if hybrid storage is detected and configure 1x4 PCIe
configuration if hybrid storage is not detected during boot up.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/7

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), caveh jalali, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#8).

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

soc/intel/tigerlake: Enable Hybrid storage mode

To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mede for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/8

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 8:

(8 comments)

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@7 
PS6, Line 7: Hybride
> remove the `e` at the end: Hybrid

Ack

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@9 
PS6, Line 9: For using
> To use

Ack

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@9 
PS6, Line 9: storage(optane)
> I think `Optane` should be capitalized as well

Ack

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@10 
PS6, Line 10: And this can be
            : configured by fit configuration which is built time.
> There are lots of words related to `configure` close together. […]

Ack

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@12 
PS6, Line 12: By enabling Hybrid Storage mode in FSP, FSP will detect Hybrid storage
> Please add one blank line above to separate paragraphs.

Ack

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@12 
PS6, Line 12: FSP
> FSP-S

Done

https://review.coreboot.org/c/coreboot/+/39232/6//COMMIT_MSG@13 
PS6, Line 13: and save configuration
            : for next boot up.
> Where does it get saved to? Also, to avoid repeating `configure`, I would use: […]

Ack

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/39232/6/src/soc/intel/tigerlake/chi... 
PS6, Line 266: 	/* Hybrid storage mode enable(1)/disable(0) */
> It would be inconsistent with the comments above, though... […]

Ack

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 8: Code-Review+1

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 9:

Rebased with new UPD header

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[caveh jalali (Code Review)]

caveh jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 9: Code-Review+1

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Caveh Jalali, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#11).

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

soc/intel/tigerlake: Enable Hybrid storage mode

To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mede for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/11

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Srinidhi N Kaushik (Code Review)]

Srinidhi N Kaushik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 11: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 12: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 12: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/39232/12//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/12//COMMIT_MSG@10 
PS12, Line 10: mede
mode

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Hello build bot (Jenkins), Caveh Jalali, Angel Pons, Nick Vaccaro, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/39232

to look at the new patch set (#13).

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

soc/intel/tigerlake: Enable Hybrid storage mode

To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/39232/13

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 13:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39232/12//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39232/12//COMMIT_MSG@10 
PS12, Line 10: mede
> mode

Ack

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

Patch Set 13: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Enable Hybrid storage mode

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39232 )

Change subject: soc/intel/tigerlake: Enable Hybrid storage mode
......................................................................

soc/intel/tigerlake: Enable Hybrid storage mode

To use Optane memory, we need to set 2x2 PCIe lane mode while we need
to set 1x4 PCIe lane mode for NVMe. The mode can be selected using
the FIT tool at build time.

By enabling hybrid storage mode in FSP, FSP will set 2x2 PCIe lane mode
if Optane memory is detected and the mode is not 2x2 and set 1x4 PCIe
lane mode if Optane memory is not detected and the mode is not 1x4
during boot up. The mode is saved in SPI NOR for next boot.

BUG=b:148604250
BRANCH=none
TEST=Build and test booting TGLRVP from NVMe and Optane
Check PCIe lane configuration.

Show all the NVMe devices
lspci -d ::0108
Show all the NVMe devices and be really verbose
lspci -vvvd ::0108
Print PCIe lane capabilities and configurations for all the NVMe devices.
lspci -vvvd ::0108 | grep -e x[124]
Print all the PCIe information of the device ae:00.0
lspci -vvvs ae:

Signed-off-by: Wonkyu Kim 
Change-Id: I25bc380697b0774cc30ad1b31ad785ee18822619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39232
Reviewed-by: Angel Pons 
Reviewed-by: Nick Vaccaro 
Reviewed-by: Srinidhi N Kaushik 
Reviewed-by: Caveh Jalali 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
2 files changed, 8 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Srinidhi N Kaushik: Looks good to me, approved
  Caveh Jalali: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index a6bcf08..d2ea0dd 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -266,6 +266,11 @@
    uint8_t DdiPort2Ddc;
    uint8_t DdiPort3Ddc;
    uint8_t DdiPort4Ddc;
+
+	/* Hybrid storage mode enable (1) / disable (0)
+	 * This mode makes FSP detect Optane and NVME and set PCIe lane mode
+	 * accordingly */
+	uint8_t HybridStorageMode;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 0dae0fe..14997c5 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -157,6 +157,9 @@
    params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
    params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;

+	/* Enable Hybrid storage auto detection */
+	params->HybridStorageMode = config->HybridStorageMode;
+
    mainboard_silicon_init_params(params);
 }